參數(shù)資料
型號(hào): LPC2157FBD100
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: Single-chip 16-bit-32-bit microcontrollers; 512 kB flash, with 32 segment x 4 LCD driver
中文描述: 32-BIT, FLASH, 60 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT407-1, LQFP-100
文件頁(yè)數(shù): 28/45頁(yè)
文件大?。?/td> 220K
代理商: LPC2157FBD100
LPC2157_2158_2
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 — 9 February 2009
28 of 45
NXP Semiconductors
LPC2157/2158
Single-chip 16-bit/32-bit microcontrollers
6.21.4
Oscillator
6.21.4.1
Internal clock
An internal oscillator provides the clock signals for the internal logic of the LCD controller
and its LCD drive signals. After power-up, pin SDA must be HIGH to guarantee that the
clock starts.
6.21.5
Timing
The LCD controller timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division of the clock frequency from either
the internal or an external clock.
Frame frequency = f
osc(ctrl)LCD
/24.
6.21.6
Display register
A display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs, and each column of the display RAM.
6.21.7
Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31. The segment output
signals are generated according to the multiplexed backplane signals and the display
latch data. When less than 32 segment outputs are required, the unused segment outputs
should be left open-circuit.
6.21.8
Backplane outputs
The LCD drive section has four backplane outputs BP0 to BP3. The backplane output
signals are generated in accordance with the selected LCD drive mode. If less than four
backplane outputs are required, the unused outputs can be left open-circuit. In the 1:3
multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent
outputs can be tied together to give enhanced drive capabilities. In the 1:2 multiplex drive
mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be
paired to increase the drive capabilities. In the static drive mode the same signal is carried
by all four backplane outputs and they can be connected in parallel for very high drive
requirements.
6.21.9
Display RAM
The display RAM is a static 32
×
4-bit RAM which stores LCD data. There is a one-to-one
correspondence between the RAM addresses and the segment outputs, and between the
individual bits of a RAM word and the backplane outputs. The first RAM column
corresponds to the 32 segments for backplane 0 (BP0). In multiplexed LCD applications
the segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
6.21.10
Data pointer
The Display RAM is addressed using the data pointer. Either a single byte or a series of
display bytes may be loaded into any location of the display RAM.
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