- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385497 > LPC2146FBD64 (NXP Semiconductors N.V.) Single-chip 16-bit-32-bit microcontrollers; up to 512 kB flash with ISP-IAP, USB 2.0 full-speed device, 10-bit ADC and DAC PDF資料下載
參數(shù)資料
| 型號(hào)： | LPC2146FBD64 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | Single-chip 16-bit-32-bit microcontrollers; up to 512 kB flash with ISP-IAP, USB 2.0 full-speed device, 10-bit ADC and DAC |
| 封裝： | LPC2141FBD64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2142FBD64<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html< |
| 文件頁數(shù)： | 24/45頁 |
| 文件大?。?/td> | 391K |
| 代理商： | LPC2146FBD64 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當(dāng)前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
LPC2141_42_44_46_48
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 12 August 2011
24 of 45
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
6.19.8
Power control
The LPC2141/42/44/46/48 supports two reduced power modes: Idle mode and
Power-down mode.
In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.
Peripheral functions continue operation during Idle mode and may generate interrupts to
cause the processor to resume execution. Idle mode eliminates power used by the
processor itself, memory systems and related controllers, and internal buses.
In Power-down mode, the oscillator is shut down and the chip receives no internal clocks.
The processor state and registers, peripheral registers, and internal SRAM values are
preserved throughout Power-down mode and the logic levels of chip output pins remain
static. The Power-down mode can be terminated and normal operation resumed by either
a reset or certain specific interrupts that are able to function without clocks. Since all
dynamic operation of the chip is suspended, Power-down mode reduces chip power
consumption to nearly zero.
Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip
RTC will enable the microcontroller to have the RTC active during Power-down mode.
Power-down current is increased with RTC active. However, it is significantly lower than in
Idle mode.
A Power Control for Peripherals feature allows individual peripherals to be turned off if
they are not needed in the application, resulting in additional power savings during active
and Idle mode.
6.19.9
APB bus
The APB divider determines the relationship between the processor clock (CCLK) and the
clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first
is to provide peripherals with the desired PCLK via APB bus so that they can operate at
the speed chosen for the ARM processor. In order to achieve this, the APB bus may be
slowed down to
1
2
to
1
4
of the processor clock rate. Because the APB bus must work
properly at power-up (and its timing cannot be altered if it does not work since the APB
divider control registers reside on the APB bus), the default condition at reset is for the
APB bus to run at
1
4
of the processor clock rate. The second purpose of the APB divider
is to allow power savings when an application does not require any peripherals to run at
the full processor rate. Because the APB divider is connected to the PLL output, the PLL
remains active (if it was running) during Idle mode.
6.20 Emulation and debugging
The LPC2141/42/44/46/48 support emulation and debugging via a JTAG serial port. A
trace port allows tracing program execution. Debugging and trace functions are
multiplexed only with GPIOs on Port 1. This means that all communication, timer and
interface peripherals residing on Port 0 are available during the development and
debugging phase as they are when the application is run in the embedded system itself.
6.20.1
EmbeddedICE
Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of
the target system requires a host computer running the debugger software and an
EmbeddedICE protocol convertor. EmbeddedICE protocol convertor converts the remote
debug protocol commands to the JTAG data needed to access the ARM core.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LPC2148FBD64 | Single-chip 16-bit-32-bit microcontrollers; up to 512 kB flash with ISP-IAP, USB 2.0 full-speed device, 10-bit ADC and DAC |
| LPC2157FBD100 | Single-chip 16-bit-32-bit microcontrollers; 512 kB flash, with 32 segment x 4 LCD driver |
| LPC2158FBD100 | Single-chip 16-bit-32-bit microcontrollers; 512 kB flash, with 32 segment x 4 LCD driver |
| LPC2194HBD64 | Single-chip 16-32-bit microcontroller; 256 kB ISP-IAP flash with 10-bit ADC and CAN |
| LPC2210FBD144 | 16-32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LPC2146FBD64,151 | 功能描述:ARM微控制器 - MCU ARM7 256KF/40KR/USB RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2146FBD64,151/REVB | 制造商:NXP Semiconductors 功能描述:LPC2146FBD64/LQFP64/TRAYB// |
| LPC2146FBD64,557 | 功能描述:ARM微控制器 - MCU 256K FL/32K RAM 10BIT ADC/DAC RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LPC2146FBD64151 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 60MHZ LQFP-64 |
| LPC2148 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。