參數(shù)資料
型號: LPC2138FBD64
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學處理器
英文描述: Single-chip 16-32-bit microcontrollers; 32-64-128-256-512 kB ISP-IAP flash with 10-bit ADC and DAC
封裝: LPC2131FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2131FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.h
文件頁數(shù): 17/45頁
文件大小: 381K
代理商: LPC2138FBD64
LPC2131_32_34_36_38
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5.1 — 29 July 2011
17 of 45
NXP Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
6.7.2
Fast I/O features available in LPC213x/01 only
Fast I/O registers are located on the ARM local bus for the fastest possible I/O timing.
All GPIO registers are byte addressable.
Entire port value can be written in one instruction.
Mask registers allow single instruction to set or clear any number of bits in one port.
6.8 10-bit ADC
The LPC2131/32 contain one and the LPC2134/36/38 contain two ADCs. These
converters are single 10-bit successive approximation ADCs with eight multiplexed
channels.
6.8.1
Features
Measurement range of 0 V to 3.3 V.
Each converter capable of performing more than 400000 10-bit samples per second.
Burst conversion mode for single or multiple inputs.
Optional conversion on transition on input pin or Timer Match signal.
Global Start command for both converters (LPC2134/36/38 only).
6.8.2
ADC features available in LPC213x/01 only
Every analog input has a dedicated result register to reduce interrupt overhead.
Every analog input can generate an interrupt once the conversion is completed.
6.9 10-bit DAC
This peripheral is available in the LPC2132/34/36/38 only. The DAC enables the
LPC2132/34/36/38 to generate variable analog output.
6.9.1
Features
10-bit digital to analog converter.
Buffered output.
Power-down mode available.
Selectable speed versus power.
6.10 UARTs
The LPC2131/32/34/36/38 each contain two UARTs. In addition to standard transmit and
receive data lines, the LPC2134/36/38 UART1 also provides a full modem control
handshake interface.
6.10.1
Features
16 B Receive and Transmit FIFOs.
Register locations conform to 16C550 industry standard.
Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B
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