參數(shù)資料
型號: LPC2134FBD64
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: Single-chip 16-32-bit microcontrollers; 32-64-128-256-512 kB ISP-IAP flash with 10-bit ADC and DAC
封裝: LPC2131FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.html<1<Always Pb-free,;LPC2131FBD64/01<SOT314-2 (LQFP64)|<<http://www.nxp.com/packages/SOT314-2.h
文件頁數(shù): 12/45頁
文件大?。?/td> 381K
代理商: LPC2134FBD64
LPC2131_32_34_36_38
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5.1 — 29 July 2011
12 of 45
NXP Semiconductors
LPC2131/32/34/36/38
Single-chip 16/32-bit microcontrollers
[1]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
[2]
5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input
function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns.
[3]
Open drain 5 V tolerant digital I/O I
2
C-bus 400 kHz specification compatible pad. It requires external pull-up to provide an output
functionality.
[4]
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog input function. If configured
for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. When configured as an ADC input, digital
section of the pad is disabled.
[5]
5 V tolerant pad providing digital I/O (with TTL levels and hysteresis and 10 ns slew rate control) and analog output function. When
configured as the DAC output, digital section of the pad is disabled.
[6]
5 V tolerant pad with built-in pull-up resistor providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control.
The pull-up resistor’s value ranges from 60 k
to 300 k
.
[7]
5 V tolerant pad providing digital input (with TTL levels and hysteresis) function only.
[8]
Pad provides special analog functionality.
[9]
When unused, the RTCX1 pin can be grounded or left floating. For lowest power leave it floating.
The other RTC pin, RTCX2, should be left floating.
P1.26/RTCK
24
[6]
I/O
RTCK —
Returned Test Clock output. Extra signal added to the JTAG port. Assists
debugger synchronization when processor frequency varies. Bidirectional pin with
internal pull-up. LOW on RTCK while RESET is LOW enables pins P1.31:26 to operate
as Debug port after reset.
TDO —
Test Data out for JTAG interface.
TDI —
Test Data in for JTAG interface.
TCK —
Test Clock for JTAG interface.
TMS —
Test Mode Select for JTAG interface.
TRST —
Test Reset for JTAG interface.
External reset input:
A LOW on this pin resets the device, causing I/O ports and
peripherals to take on their default states, and processor execution to begin at address
0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Ground:
0 V reference.
P1.27/TDO
P1.28/TDI
P1.29/TCK
P1.30/TMS
P1.31/TRST
RESET
64
[6]
60
[6]
56
[6]
52
[6]
20
[6]
57
[7]
O
I
I
I
I
I
XTAL1
XTAL2
RTCX1
RTCX2
V
SS
62
[8]
61
[8]
3
[9]
5
[9]
6, 18,
25, 42,
50
59
I
O
I
O
I
V
SSA
I
Analog ground:
0 V reference. This should nominally be the same voltage as V
SS
, but
should be isolated to minimize noise and error.
3.3 V power supply:
This is the power supply voltage for the core and I/O ports.
V
DD
23, 43,
51
7
I
V
DDA
I
Analog 3.3 V power supply:
This should be nominally the same voltage as V
DD
but
should be isolated to minimize noise and error. This voltage is used to power the
on-chip PLL.
ADC reference:
This should be nominally the same voltage as V
DD
but should be
isolated to minimize noise and error. Level on this pin is used as a reference for A/D
and D/A convertor(s).
RTC power supply:
3.3 V on this pin supplies the power to the RTC.
VREF
63
I
VBAT
49
I
Table 3.
Symbol
Pin description
…continued
Pin
Type
Description
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