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參數資料
| 型號： | LPC2105FBD48 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數學處理器 |
| 英文描述： | Single-chip 32-bit microcontrollers; 128 kB ISP-IAP flash with 16-32-64 kB RAM |
| 封裝： | LPC2104FBD48/01<SOT313|<<<1<Always Pb-free,;LPC2105FBD48/01<SOT313|<<<1<Always Pb-free,;LPC2106FBD48/01<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313 |
| 文件頁數： | 17/41頁 |
| 文件大小： | 188K |
| 代理商： | LPC2105FBD48 |
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LPC2104_2105_2106_7
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 07 — 20 June 2008
17 of 41
NXP Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
Standard modem interface signals included on UART 1.
6.10.2
UART features available in LPC2104/2105/2106/01 only
Compared to previous LPC2000 microcontrollers, UARTs in LPC2104/2105/2106/01
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in
hardware.
Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
Autobauding.
Auto-CTS/RTS flow-control fully implemented in hardware.
6.11 I
2
C-bus serial I/O controller
I
2
C is a bidirectional bus for inter-IC control using only two wires: a serial clock line (SCL),
and a serial data line (SDA). Each device is recognized by a unique address and can
operate as either a receiver-only device (e.g. an LCD driver or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. I
2
C is a multi-master bus, it can be
controlled by more than one bus master connected to it.
The I
2
C-bus implemented in LPC2104/2105/2106 supports bit rate up to 400 kbit/s (Fast
I
2
C-bus).
6.11.1
Features
Standard I
2
C compliant bus interface.
Easy to configure as Master, Slave or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
C-bus may be used for test and diagnostic purposes.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LPC2105FBD48/00 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM |
| LPC2105FBD48/01 | 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, LQFP-48 制造商:NXP Semiconductors 功能描述:MCU, 16BIT/32BIT, 60MHZ, LQFP-48, Controller Family/Series:LPC2100, Core Size:16bit / 32bit, No. of I/O's:32, Supply Voltage Min:1.65V, Supply Voltage Max:1.95V, Digital IC Case Style:LQFP, No. of Pins:48, Program Memory Size:128KB, |
| LPC2105FBD48/01,15 | 功能描述:ARM微控制器 - MCU 128K FL/32K RAM/2 UART/I2C/SPI RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數據總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數據 RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LPC2106 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single-chip 32-bit microcontrollers; 128 kB ISP/IAP flash with 16/32/64 kB RAM |
| LPC2106BBD48 | 制造商:NXP Semiconductors 功能描述:Microcontroller,LPC2106BBD48 60 MHz |
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