參數(shù)資料
型號(hào)： LPC1346FHN33,551
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 9/77頁(yè)
文件大小： 0K
描述： MCU 32BIT ARM 48KB FLASH 32HVQFN
標(biāo)準(zhǔn)包裝： 260
系列： LPC13xx
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 72MHz
連通性： I²C，Microwire，SPI，SSI，SSP，UART/USART，USB
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 26
程序存儲(chǔ)器容量： 48KB（48K x 8）
程序存儲(chǔ)器類型： 閃存
EEPROM 大小： 4K x 8
RAM 容量： 10K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤
包裝： 托盤
LPC1315_16_17_45_46_47
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 20 September 2012
17 of 77
NXP Semiconductors
LPC1315/16/17/45/46/47
32-bit ARM Cortex-M3 microcontroller
[1]
Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled;
F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
[2]
See Figure 33 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to
reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down
mode.
[3]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 32).
[4]
I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode Plus.
[5]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 32);
includes high-current output driver.
[6]
5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input.
When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 32); includes
programmable digital input glitch filter.
[7]
WAKEUP pin. 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and
analog input. When configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 32);
includes digital input glitch filter.
[8]
When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). XTALOUT should be left floating.
VREFP
64
-
ADC positive reference voltage: This should be nominally
the same voltage as VDDA but should be isolated to
minimize noise and error. Level on this pin is used as a
reference for ADC. This pin should be tied to 3.3 V if the
ADC is not used.
VSSA
55
-
Analog ground: 0 V reference. This should nominally be
the same voltage as VSSProduct data sheet but should be
isolated to minimize noise and error.
VDD
10;
33;
58
8;
44
6;
29
-
Supply voltage to the internal regulator and the external
rail. On LQFP48 and HVQFN33 packages, this pin is also
connected to the 3.3 V ADC supply and reference
voltage.
VSS
7;
54
5;
41
33
-
Ground.
Table 3.
Pin description (LPC1315/16/17 - no USB)
Symbol
LQ
FP6
4
LQ
FP4
8
HVQFN
3
Re
set
st
ate
[1
]
Ty
p
e
Description
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