參數(shù)資料
型號(hào)： LPC1313FHN33/01,55
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 16/74頁(yè)
文件大小： 0K
描述： MCU CORTEX M3 32KB FLASH 32HVQFN
標(biāo)準(zhǔn)包裝： 260
系列： LPC13xx
核心處理器： ARM? Cortex?-M3
芯體尺寸： 32-位
速度： 72MHz
連通性： I²C，Microwire，SPI，SSI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，WDT
輸入/輸出數(shù)： 28
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 8K x 8
電壓 - 電源 (Vcc/Vdd)： 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 32-VQFN 裸露焊盤(pán)
包裝： 托盤(pán)
其它名稱： 568-8375
LPC1311_13_42_43
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 5 — 6 June 2012
23 of 74
NXP Semiconductors
LPC1311/13/42/43
32-bit ARM Cortex-M3 microcontroller
7.14 General purpose external event counter/timers
The LPC1311/13/42/43 includes two 32-bit counter/timers and two 16-bit counter/timers.
The counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.14.1 Features
A 32-bit/16-bit counter/timer with a programmable 32-bit/16-bit prescaler.
Counter or timer operation.
One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event may also generate an interrupt.
Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.15 System tick timer
The ARM Cortex-M3 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval, normally set to 10 ms.
7.16 Watchdog timer
Remark: The standard Watchdog timer is available on parts LPC1311/13/42/43.
The purpose of the watchdog is to reset the microcontroller within a selectable time
period. When enabled, the watchdog will generate a system reset if the user program fails
to ‘feed’ (or reload) the watchdog within a predetermined amount of time.
7.16.1 Features
Internally resets chip if not periodically reloaded.
Debug mode.
Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
Incorrect/incomplete feed sequence causes reset/interrupt if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
相關(guān)PDF資料
PDF描述
C8051F561-IQ IC 8051 MCU 32K FLASH 32-QFP
P80C32X2FN,112 IC 80C51 MCU 256 ROMLESS 40DIP
EFM32TG822F32 IC MCU 32BIT 32KB FLASH 48LQFP
LPC1313FHN33,551 IC MCU 32BIT 32KB FLASH 33HVQFN
P80C32SBAA,512 IC 80C51 MCU 8BIT ROMLESS 44PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LPC1313FHN33551 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU ARM 72MHZ HVQFN-33
LPC1313FHN33CP3264 制造商:NXP Semiconductors 功能描述:- Trays
LPC1313FHN33CP3265 制造商:NXP Semiconductors 功能描述:- Trays
LPC1315 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M3 microcontroller; up to 64 kB flash; up to 12 kB SRAM; USB device; USART; EEPROM
LPC1315FBD48 制造商:NXP Semiconductors 功能描述:MCU 32BIT ARM CORTEX-M3 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM CORTEX-M3, 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 32BIT, ARM CORTEX-M3, 48LQFP, Controller Family/Series:LPC13xx, Core Size:32bit, No. of I/O's:40, Supply Voltage Min:2V, Supply Voltage Max:3.6V, Digital IC Case Style:LQFP, No. of Pins:48, Program Memory Size:32KB, EEPROM , RoHS Compliant: Yes
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*