參數(shù)資料
型號(hào)： LPC1224FBD64/101,1
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 20/61頁(yè)
文件大小： 0K
描述： MCU 32BIT 32K FLASH 4K 64-LQFP
產(chǎn)品培訓(xùn)模塊： LPC1200 Series for Industrial Control
標(biāo)準(zhǔn)包裝： 160
系列： LPC1200
核心處理器： ARM? Cortex?-M0
芯體尺寸： 32-位
速度： 45MHz
連通性： I²C，IrDA，Microwire，SPI，SSI，SSP，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，DMA，POR，WDT
輸入/輸出數(shù)： 55
程序存儲(chǔ)器容量： 32KB（32K x 8）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-LQFP
包裝： 托盤
其它名稱： 568-5155
LPC1224FBD64/201
LPC1224FBD64/201,1
LPC122X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 26 August 2011
27 of 61
NXP Semiconductors
LPC122x
32-bit ARM Cortex-M0 microcontroller
An external pull-up resistor is required on the RESET pin if Deep power-down mode is
used.
7.19.3 Brownout detection
The LPC122x includes four levels for monitoring the voltage on the VDD(3V3) pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to
the NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the
NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading
a dedicated status register. An additional threshold level can be selected to cause a
forced reset of the chip.
7.19.4 Code security (Code Read Protection - CRP)
This feature of the LPC122x allows user to enable different levels of security in the system
so that access to the on-chip flash and use of the SWD and ISP can be restricted. When
needed, CRP is invoked by programming a specific pattern into a dedicated flash location.
IAP commands are not affected by the CRP.
There are three levels of Code Read Protection:
1. CRP1 disables access to chip via the SWD and allows partial flash update (excluding
flash sector 0) using a limited set of the ISP commands. This mode is useful when
CRP is required and flash field updates are needed but all sectors can not be erased.
2. CRP2 disables access to chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected fully disables any access to chip via
the SWD pins and the ISP. This mode effectively disables ISP override using PIO0_12
pin, too. It is up to the user’s application to provide (if needed) flash update
mechanism using IAP calls or call reinvoke ISP command to enable flash update via
UART0.
In addition to the three CRP levels, sampling of pin PIO0_12 for valid user code can be
disabled.
7.19.5 APB interface
The APB peripherals are located on one APB bus.
7.19.6 AHB-Lite
The AHB-Lite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the Boot ROM.
7.19.7 External interrupt inputs
All GPIO pins can be level or edge sensitive interrupt inputs.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
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LPC1224FBD64121 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
LPC1224FBD64-121 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Up to 128 KB Flash and configurable peripherals for industrial control
LPC1225 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller; up to 128 kB flash and 8 kB SRAM
LPC1225FBD48/301 制造商:NXP Semiconductors 功能描述:MCU 64K FLASH CORTEX-M0 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 64K FLASH, CORTEX-M0, 48LQFP 制造商:NXP Semiconductors 功能描述:MCU, 64K FLASH, CORTEX-M0, 48LQFP, Controller Family/Series:LPC1200, Core Size:3
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