參數(shù)資料
型號(hào): LPC11U24FHN33/401,
廠商: NXP Semiconductors
文件頁(yè)數(shù): 14/74頁(yè)
文件大?。?/td> 0K
描述: MCU USB 33HVQFN
產(chǎn)品培訓(xùn)模塊: Code Density for LPC11xx
標(biāo)準(zhǔn)包裝: 260
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 4K x 8
RAM 容量: 10K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤(pán)
包裝: 托盤(pán)
其它名稱: 568-8524
LPC11U24FHN33/401,-ND
LPC11U2X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
21 of 74
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
Four match registers per timer that allow:
Continuous operation with optional interrupt generation on match.
Stop timer on match with optional interrupt generation.
Reset timer on match with optional interrupt generation.
Up to four external outputs corresponding to match registers, with the following
capabilities:
Set LOW on match.
Set HIGH on match.
Toggle on match.
Do nothing on match.
The timer and prescaler can be configured to be cleared on a designated capture
event. This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
7.15 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.16 Windowed WatchDog Timer (WWDT)
The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
7.16.1 Features
Internally resets chip if not periodically reloaded during the programmable time-out
period.
Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
Optional warning interrupt can be generated at a programmable time before watchdog
time-out.
Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
Incorrect feed sequence causes reset or interrupt, if enabled.
Flag to indicate watchdog reset.
Programmable 24-bit timer with internal prescaler.
Selectable time period from (Tcy(WDCLK) 256 4) to (Tcy(WDCLK) 224 4) in
multiples of Tcy(WDCLK) 4.
The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.
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LPC11U34FBD48 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:32-bit ARM Cortex-M0 microcontroller up to 128 kB flash up to 12 kB SRAM and 4 kB EEPROM USB device USART
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