參數(shù)資料
型號(hào): LPC11U23FBD48/301,
廠商: NXP Semiconductors
文件頁數(shù): 43/74頁
文件大小: 0K
描述: MCU USB 48LQFP
產(chǎn)品培訓(xùn)模塊: Code Density for LPC11xx
標(biāo)準(zhǔn)包裝: 250
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,SPI,SSI,SSP,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 24KB(24K x 8)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-LQFP
包裝: 托盤
其它名稱: 568-8520
LPC11U23FBD48/301,-ND
LPC11U2X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
48 of 74
NXP Semiconductors
LPC11U2x
32-bit ARM Cortex-M0 microcontroller
10.6 SSP interface
[1]
Tcy(clk) = (SSPCLKDIV (1 + SCR) CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate Tcy(clk) is a function of the
main clock frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register),
and the SPI CPSDVSR parameter (specified in the SPI clock prescale register).
[2]
Tamb = 40 C to 85 C.
[3]
Tcy(clk) = 12 Tcy(PCLK).
[4]
Tamb = 25 C; for normal voltage supply range: VDD = 3.3 V.
Table 16.
Dynamic characteristics of SPI pins in SPI mode
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SPI master (in SPI mode)
Tcy(clk)
clock cycle time
full-duplex mode
50
-
ns
when only transmitting [1]
40
ns
tDS
data set-up time
in SPI mode
2.4 V
V
DD 3.6 V
15
-
ns
2.0 V
V
DD < 2.4 V
20
ns
1.8 V
V
DD < 2.0 V
24
-
ns
tDH
data hold time
in SPI mode
0-
-
ns
tv(Q)
data output valid time in SPI mode
--
10
ns
th(Q)
data output hold time in SPI mode
0-
-
ns
SPI slave (in SPI mode)
Tcy(PCLK)
PCLK cycle time
20
-
ns
tDS
data set-up time
in SPI mode
0-
-
ns
tDH
data hold time
in SPI mode
3
T
cy(PCLK) + 4
-
ns
tv(Q)
data output valid time in SPI mode
--
3
T
cy(PCLK) + 11
ns
th(Q)
data output hold time in SPI mode
--
2
T
cy(PCLK) + 5
ns
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