參數(shù)資料
型號: LPC11U12FHN33/201,
廠商: NXP Semiconductors
文件頁數(shù): 8/72頁
文件大小: 0K
描述: IC MCU 32BIT 16K 33HVQFN
產(chǎn)品培訓模塊: Code Density for LPC11xx
標準包裝: 260
系列: LPC11Uxx
核心處理器: ARM? Cortex?-M0
芯體尺寸: 32-位
速度: 50MHz
連通性: I²C,Microwire,智能卡,SPI,SSP,UART/USART,USB
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 26
程序存儲器容量: 16KB(16K x 8)
程序存儲器類型: 閃存
RAM 容量: 6K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉換器: A/D 8x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-VQFN 裸露焊盤
包裝: 托盤
其它名稱: 568-8559
LPC11U1X
All information provided in this document is subject to legal disclaimers.
NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.2 — 11 March 2014
16 of 72
NXP Semiconductors
LPC11U1x
32-bit ARM Cortex-M0 microcontroller
7.
Functional description
7.1 On-chip flash programming memory
The LPC11U1x contain up to 32 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP)
via the on-chip boot loader software.
7.2 SRAM
The LPC11U1x contain a total of 6 kB on-chip static RAM memory.
7.3 On-chip ROM
The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
In-System Programming (ISP) and In-Application Programming (IAP) support for flash
programming
Power profiles for configuring power consumption and PLL settings
32-bit integer division routines
7.4 Memory map
The LPC11U1x incorporates several distinct memory regions, shown in the following
figures. Figure 5 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals.
The APB peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals.
Each peripheral of either type is allocated 16 kB of space. This allows simplifying the
address decoding for each peripheral.
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