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參數(shù)資料
| 型號： | LPC11E14FHN33/401, |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 32K 32HVQFN |
| 產(chǎn)品培訓(xùn)模塊： | Code Density for LPC11xx |
| 標(biāo)準包裝： | 260 |
| 系列： | LPC11Exx |
| 核心處理器： | ARM? Cortex?-M0 |
| 芯體尺寸： | 32-位 |
| 速度： | 50MHz |
| 連通性： | I²C，Microwire，SPI，SSI，SSP，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，WDT |
| 輸入/輸出數(shù)： | 28 |
| 程序存儲器容量： | 32KB（32K x 8） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 4K x 8 |
| RAM 容量： | 10K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.8 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 8x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VQFN 裸露焊盤 |
| 包裝： | 托盤 |
| 其它名稱： | 568-8583 |
ES_LPC11E1X
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Errata sheet
Rev. 2 — 1 February 2013
3 of 8
NXP Semiconductors
ES_LPC11E1x
Errata sheet LPC11E1x
1.
Product identification
The LPC11E1x devices typically have the following top-side marking:
LPC11E1x
/xxx
xxxxxxx
xxYYWWxR[x]
The last letter in the last line (field ‘R’) will identify the device revision. This Errata Sheet
covers the following revisions of the LPC11E1x:
Field ‘YY’ states the year the device was manufactured. Field ‘WW’ states the week the
device was manufactured during that year.
2.
Errata overview
Table 1.
Device revision table
Revision identifier (R)
Revision description
‘B’
Initial device revision
Table 2.
Errata summary table
Functional
problems
Short description
Revision identifier
Detailed description
ADC.1
A/D Global Data register should not be used with burst
mode or hardware triggering.
‘B’
I2C.1
In the slave-transmitter mode, the device set in the
monitor mode must write a dummy value of 0xFF into
the DAT register.
‘B’
Table 3.
AC/DC deviations table
AC/DC
deviations
Short description
Revision identifier
Detailed description
n/a
Table 4.
Errata notes table
Errata notes
Short description
Revision identifier
Detailed description
Note.1
During power-up, an unexpected glitch (low pulse)
could occur on the port pins as the VDD supply ramps
up.
‘B’
Note.2
For LPC11E14/401 devices with date codes 1238 and
before, the 2 kB SRAM located at address
0x20000000-0x20000800 is not available.
‘B’
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