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參數資料
| 型號： | LP62S2048AM-55LLT |
| 廠商： | AMIC Technology Corporation |
| 英文描述： | 256K X 8 BIT LOW VOLTAGE CMOS SRAM |
| 中文描述： | 256K × 8位低電壓CMOS的SRAM |
| 文件頁數： | 9/17頁 |
| 文件大小： | 190K |
| 代理商： | LP62S2048AM-55LLT |
LP62S2048A-T Series
PRELIMINARY
(June, 2002, Version 0.0)
9
AMIC Technology, Inc.
Timing Waveforms (continued)
Read Cycle 4
(1)
t
RC
Address
CE2
D
OUT
t
AA
t
OE
t
OLZ5
t
ACE1
t
CLZ15
t
ACE2
t
CLZ25
t
CHZ25
t
OHZ5
t
CHZ15
t
OH
OE
CE1
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled CE1 = V
IL
and CE2 = V
IH
.
3. Address valid prior to or coincident with CE1 transition low.
4. OE = V
IL
.
5. Transition is measured
±
500mV from steady state. This parameter is sampled and not 100% tested.
6. CE2 is high.
7. CE1 is low.
8. Address valid prior to or coincident with CE2 transition high.
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