
LP621024D Series 
128K X 8 BIT CMOS SRAM  
(August, 2001, Version 1.0) 
   1                                       
AMIC Technology, Inc.
Features 
n
 Single +5V power supply 
n
 Access times: 55/70 ns (max.) 
n
 Current: 
     Very low power version: Operating: 70mA  (max.) 
n
 Full static operation, no clock or refreshing required 
n
 All inputs and outputs are directly TTL-compatible 
Standby: 
25
μ
A (max.) 
n
 Common I/O using three-state output 
n
 Output enable and two chip enable inputs for easy 
application 
n
 Data retention voltage: 2V (min.) 
n
 Available in 32-pin DIP, SOP TSOP and TSSOP 
(8 X 13.4mm) packages 
General Description
The LP621024D is a low operating current 1,048,576-bit 
static random access memory organized as 131,072 
words by 8 bits and operates on a single 5V power 
supply.  
Inputs and three-state outputs are TTL compatible and 
allow for direct interfacing with common system bus 
structures. 
Two chip enable inputs are provided for POWER-DOWN 
and device enable and an output enable input is included 
for easy interfacing. 
Data retention is guaranteed at a power supply voltage 
as low as 2V. 
Pin Configurations 
n
 DIP 
n
 SOP 
n
 TSOP/(TSSOP) 
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
A10
A9
A8
A13
CE2
A15
VCC
A11
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O
1
I/O
2
I/O
3
I/O
4
GND
I/O
5
I/O
6
I/O
7
I/O
8
A10
A9
A8
A13
CE2
A15
VCC
A11
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
OE
L
(
1
16
17
32
Pin No.
Pin
Name
Pin No.
Pin
Name
1
2
A9
3
4
5
6
7
8
9
10
11
12
13
14
30
29
28
27
26
25
24
22
19
21
20
23
18
17
A8
A13
CE2
A15
VCC
NC
I/O
8
A16
A14
A12
A7
A6
A3
A2
A1
A0
I/O
1
I/O
2
GND
I/O
4
I/O
5
I/O
6
I/O
7
I/O
3
A11
WE
CE1
15
16
31
32
A5
A4
A10
OE
CE1
WE
CE1
WE