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| 型號： | LP5551 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PowerWise⑩ Technology Compliant Energy Management Unit |
| 中文描述： | ⑩技術(shù)兼容的PowerWise能源管理單元 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大小： | 3081K |
| 代理商： | LP5551 |
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N-Well Bias Characteristics
values and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction
temperature range for operation, -40 to +125°C. (Notes 2, 7, 8)
Unless otherwise noted, V
DD_A, _D
, V
PVDD1,2
, RESETN, ENABLE = 3.6V. Typical
Symbol
V
OFFSET
Accuracy
Parameter
Output Voltage Offset Tolerance
Conditions
V
AVS
= 1.2 V
V
OFFSET
= -0.3 V
Iout = 10 μA
2.7
≤
V
DD_A, _D
, P
VDD1,2
≤
5.5 V
I
OUT
= 10 uA,V
OFFSET
= -0.315
2.7 V
≤
V
DD_A, _D
, P
VDD1,2
≤
5.5 V
V
DD_A, _D
, P
VDD1,2
= 3.6 V
VAVS = 1.2 V
0.1 uA
≤
IOUT
≤
10 uA
Programming Resolution: See
Register Table
Min
-0.363
Typ
-0.3
Max
-0.266
Units
V
Line Regulation
0.321
%/V
Load Regulation
-0.107
%/mA
V
OFFSET
Range
I
Q
I
SOURCE/SINK
Programmable Output Voltage
Offset: Referenced to V
AVS
Quiescent Current
-0.315
0
1
V
3
50
uA
Output Sourcing and Sinking
Capability
V
DD_A, _D
, P
VDD1,2
= 3.6 V,
V
OFFSET
= 1 V
V
OFFSET
> V
OFFSET(NOM)
- 15 mV
Steady State
V
DD_A, _D
, P
VDD1,2
= 3.6 V,
V
NWELL
= 0 V
Steady State
V
DD_A, _D
, P
VDD1,2
= 3.6 V,
V
NWELL
= V
DD_A
Steady State
0 μA
≤
I
OUT
≤
3 uA
mA
I
SC (SOURCE)
Output Source Short Circuit Limit
42
mA
I
SC (SINK)
Output Sink Short Circuit Limit
65
mA
C
LOAD
Output Capacitance Of Load
0.1
1
5
nF
P-Well Characteristics
and limits appearing in normal type apply for TJ = 25°C. Limits appearing in boldface type apply over the entire junction temperature
range for operation, -40 to +125°C. (Notes 2, 7, 8)
Unless otherwise noted, V
DD_A, _D
, V
PVDD1,2
, RESETN, ENABLE = 3.6V. Typical values
Symbol
V
OUT
Accuracy
Parameter
Output Voltage Tolerance
Conditions
V
OUT
= 0 V
I
OUT
= 10 μA
2.7
≤
V
DD_A, _D
, P
VDD1,2
≤
5.5 V
Bias Current Control bits = 00
I
OUT
= 10 uA
V
OUT
= 0.3 V
2.7V
≤
V
DD_A, _D
, P
VDD1,2
≤
5.5 V
V
DD_A, _D
, P
VDD1,2
= 3.6 V
V
OUT
= 0.3 V
0.1 uA
≤
I
OUT
≤
10 uA
0 mA
≤
I
OUT
≤
10 uA
Programming Resolution: See
Register Table
IOUT = 0, P-well Bias Current Control
bits = 00
Min
-0.035
Typ
0
Max
0.035
Units
V
Line Regulation
0.159
%/V
Load Regulation
0.011
%/μA
V
OUT
Range
Programmable Output Voltage
Offset:
Referenced to Ground
-1
0
0.3
V
I
Q
Quiescent Current
150
270
uA
9
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