
I
ALED
ALED current
tolerance
I
ALED
set to 13.2 mA
11.9
-10
13.2
14.5
+10
mA
%
LOGIC INTERFACE CHARACTERISTICS
Symbol
Parameter
Logic Input SS/SDA, SI/A0, SCK/SCL, IF_SEL
V
IL
Input Low Level
V
IH
Input High Level
I
I
Logic Input
Current
f
SCK/SCL
Clock Frequency
Condition
Min
Typ
Max
Units
0.2*V
DDIO
1.0
V
0.8*V
DDIO
-1.0
V
μA
I
2
C
400
13
kHz
SPI Mode,
V
DDIO > 1.8V
(Note 13)
SPI Mode,
1.65V
≤
V
DDIO
< 1.8V
MHz
5
MHz
Logic Input NRST
V
IL
V
IH
I
I
Input Low Level
0.5
V
Input High Level
1.2
-1.0
V
Logic Input
Current
Reset Pulse Width
1.0
μA
t
NRST
Logic Output SO
V
OL
10
μs
Output Low Level I
SO
= 3 mA
V
DDIO
> 1.8V
I
SO
= 2 mA
1.65V
≤
V
DDIO
< 1.8V
0.3
0.5
V
0.3
0.5
V
OH
Output High Level I
SO
= -3 mA
V
DDIO
> 1.8V
I
SO
= -2 mA
1.65V
≤
V
DDIO
< 1.8V
V
SO
= 2.8V
V
DDIO
-
0.5
V
DDIO
-
0.5
V
DDIO
-
0.3
V
V
DDIO
-
0.3
I
L
Output Leakage
Current
1.0
μA
Logic Output SDA
V
OL
Output Low Level I
SDA
= 3 mA
0.3
0.5
V
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2:
All voltages are with respect to the potential at the GND pins.
Note 3:
Battery/Charger voltage should be above 6V no more than 10% of the operational lifetime.
Note 4:
Voltage tolerance of LP55281 above 6.0V relies on fact that V
and V
(2.8V) are available (ON) at all conditions. If V
DD1
and V
DD2
are not available
(ON) at all conditions, National Semiconductor
does not guarantee any parameters or reliability for this device.
Note 5:
Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
J
= 160°C (typ.) and disengages at T
J
= 140°C (typ.)
Note 6:
For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip
Scale Package or National Semiconductor Application Note AN1412 : Micro SMDxt Wafer Level Chip Scale Package.
Note 7:
The Human Body Model is a 100 pF capacitor discharged through a 1.5 k
resistor into each pin. MIL-STD-883 3015.7
Note 8:
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
A-MAX
) is dependent on the maximum operating junction temperature (T
= 125°C), the maximum power
dissipation of the device in the application (P
), and the junction-to-ambient thermal resistance of the part/package in the application (
θ
JA
), as given by the
following equation: T
A-MAX
= T
J-MAX-OP
- (θ
JA
x P
D-MAX
).
Note 9:
Junction-to-Ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 10:
Min and Max limits are guaranteed by design, test or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 11:
Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 12:
V
DDA
output is not recommended for external use.
Note 13:
Data guaranteed by design
Note 14:
When V
IN
rises above V
OUT
+ V
SCHOTTKY
, V
OUT
starts to follow the V
IN
voltage rise so that V
OUT
= V
IN
- V
SCHOTTKY
7
www.national.com
L