參數資料
型號： LP3958TLX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 顯示驅動器
英文描述： Lighting Management Unit with High Voltage Boost Converter
中文描述： LED DISPLAY DRIVER, PBGA25
封裝： 2.54 X 2.54 MM, 0.60 MM HEIGHT, 0.50 MM PITCH, LEAD FREE, MICRO SMD PACKAGE-25
文件頁數： 19/28頁
文件大?。?/td> 1091K
代理商： LP3958TLX
I
2
C Compatible Interface
I
2
C SIGNALS
The SCL pin is used for the I
2
C clock and the SDA pin is
used for bidirectional data transfer. Both these signals need
a pull-up resistor according to I
2
C specification.
I
2
C DATA VALIDITY
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data
line can only be changed when CLK is LOW.
20175549
I
2
C Signals: Data Validity
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from
LOW to HIGH while SCL is HIGH. The I
2
C master always
generates START and STOP bits. The I
2
C bus is considered
to be busy after START condition and free after STOP con-
dition. During data transmission, I
2
C master can generate
repeated START conditions. First START and repeated
START conditions are equivalent, function-wise.
20175550
I
2
C Start and Stop Conditions
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the
acknowledge clock pulse. The receiver must pull down the
SDA line during the 9
th
clock pulse, signifying an acknowl-
edge. A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LP3958
address is 59H (101 1001b). For the eighth bit, a “0” indi-
cates a WRITE and a “1” indicates a READ. This means that
the first byte is B2H for WRITE and B3H for READ. The
second byte selects the register to which the data will be
written. The third byte contains data to write to the selected
register.
20175551
I
2
C Chip Address
Register changes take an effect at the SCL rising edge
during the last ACK from slave.
L
www.national.com
19
相關PDF資料
PDF描述
LP3971 POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS
LP3971SQ-A514 POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS
LP3971SQ-B410 POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS
LP3971SQX-A514 POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS
LP3971SQX-B410 POWER MANAGEMENT UNIT FOR ADVANCED APPLICATION PROCESSORS
相關代理商/技術參數
參數描述
LP3958TLX/NOPB 功能描述:LED照明驅動器 RoHS:否 制造商:STMicroelectronics 輸入電壓:11.5 V to 23 V 工作頻率: 最大電源電流:1.7 mA 輸出電流: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:SO-16N
LP395Z 功能描述:兩極晶體管 - BJT RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2
LP395Z 制造商:Texas Instruments 功能描述:POWER TRANSISTOR TO-92-3 395
LP395Z/LFT1 功能描述:兩極晶體管 - BJT RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2
LP395Z/LFT2 功能描述:兩極晶體管 - BJT RoHS:否 制造商:STMicroelectronics 配置: 晶體管極性:PNP 集電極—基極電壓 VCBO: 集電極—發(fā)射極最大電壓 VCEO:- 40 V 發(fā)射極 - 基極電壓 VEBO:- 6 V 集電極—射極飽和電壓: 最大直流電集電極電流: 增益帶寬產品fT: 直流集電極/Base Gain hfe Min:100 A 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:PowerFLAT 2 x 2
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