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參數(shù)資料
| 型號： | LP3954 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Advanced Lighting Management Unit |
| 中文描述： | 高級照明管理單位 |
| 文件頁數(shù)： | 32/56頁 |
| 文件大?。?/td> | 5801K |
| 代理商： | LP3954 |
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I
2
C COMPATIBLE INTERFACE
I
2
C Signals
In I
2
C mode the LP3954 pin SCK is used for the I
2
C clock SCL
and the pin SS is used for the I
2
C data signal SDA. Both these
signals need a pull-up resistor according to I
2
C specification.
SI pin is the address select pin. I
2
C address for LP3954 is 54h
when SI = 0 and 55h when SI = 1. Unused pin SO can be left
unconnected.
I
2
C Data Validity
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, state of the data line
can only be changed when CLK is LOW.
20132249
I
2
C Signals: Data Validity
I
2
C Start and Stop Conditions
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transitioning from HIGH to LOW while SCL line is HIGH.
STOP condition is defined as the SDA transitioning from LOW
to HIGH while SCL is HIGH. The I
2
C master always generates
START and STOP bits. The I
2
C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, I
2
C master can generate repeated START
conditions. First START and repeated START conditions are
equivalent, function-wise.
20132250
Transferring Data
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
th
clock pulse, signifying an acknowledge. A
receiver which has been addressed must generate an ac-
knowledge after each byte has been received.
After the START condition, the I
2
C master sends a chip ad-
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LP3954 address is
54h or 55H as selected with SI pin. For the eighth bit, a “0”
indicates a WRITE and a “1” indicates a READ. The second
byte selects the register to which the data will be written. The
third byte contains data to write to the selected register.
20132251
I
2
C Chip Address
Register changes take an effect at the SCL rising edge during
the last ACK from slave.
20132252
w = write (SDA = “0”)
r = read (SDA = “1”)
ack = acknowledge (SDA pulled down by either master or slave)
rs = repeated start
id = 7-bit chip address, 54h (SI=0) or 55h (SI=1) for LP3954.
I
2
C Write Cycle
www.national.com
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LP3954RL | Advanced Lighting Management Unit |
| LP3954RLX | Advanced Lighting Management Unit |
| LP3954TL | Advanced Lighting Management Unit |
| LP3954TLX | Advanced Lighting Management Unit |
| LP3958 | Lighting Management Unit with High Voltage Boost Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LP39542 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Lighting Management Unit |
| LP39542RL | 制造商:Texas Instruments 功能描述:IC, LIGHTING MGNT UNIT, SMD |
| LP39542RL/NOPB | 功能描述:LED照明驅(qū)動器 RoHS:否 制造商:STMicroelectronics 輸入電壓:11.5 V to 23 V 工作頻率: 最大電源電流:1.7 mA 輸出電流: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SO-16N |
| LP39542RLX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Advanced Lighting Management Unit |
| LP39542RLX/NOPB | 功能描述:LED照明驅(qū)動器 RoHS:否 制造商:STMicroelectronics 輸入電壓:11.5 V to 23 V 工作頻率: 最大電源電流:1.7 mA 輸出電流: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SO-16N |
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