參數(shù)資料
型號: LP3950SLX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 顯示驅動器
英文描述: Color LED Driver with Audio Synchronizer
中文描述: LED DISPLAY DRIVER, QCC32
封裝: 4.50 X 5.50 MM, 0.80 MM HEIGHT, 0.50 MM PITCH, CSP-32
文件頁數(shù): 10/31頁
文件大小: 1085K
代理商: LP3950SLX
SPI Timing Parameters
V
DD1
= V
DD2
= V
DDA
= 2.70V to 2.90V, V
DDIO
= 1.80V to V
DD1,2
V
Symbol
Parameter
Limit
Units
Min
80
40
40
40
40
0
20
Max
1
2
3
4
5
6
7
8
9
10
11
12
Cycle Time
Enable Lead Time
Enable Lag Time
Clock Low Time
Clock High Time
Data Setup Time
Data Hold Time
Data Access Time
Output Disable Time
Output Data Valid
Output Data Hold Time
SS Inactive Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
27
27
37
0
15
Note:
Data guaranteed by design.
I
2
C Compatible Interface
I
2
C SIGNALS
In I
2
C compatible mode, the LP3950 pin SCL is used for the
I
2
C clock and the SDA pin is used for the I
2
C data. Both
these signals need a pull-up resistor according to I
2
C speci-
fication. The values of the pull-up resistors are determined
by the capacitance of the bus (typ.
A
1.8k). Signal timing
specifications are shown in
Table I
2
C Timing Parameters
.
Unused pin SO can be left unconnected and pin SI must be
connected to V
or GND (address selector). Maximum bit
rate is 400 kbit/s (V
1.80V to V
DD1,2
V). I
2
C compatible
interface can be used down to 1.65 V
DDIO
with maximum bit
rate of 200 kbit/s.
I
2
C DATA VALIDITY
The data on the SDA line must be stable during the HIGH
period of the clock signal (SCL). In other words, state of the
data line can only be changed when CLK is LOW.
I
2
C START AND STOP CONDITIONS
START and STOP bits classify the beginning and the end of
the I
2
C session. START condition is defined as SDA signal
transition from HIGH to LOW while SCL line is HIGH. STOP
condition is defined as the SDAtransition from LOW to HIGH
while SCL is HIGH. The I
2
C master always generates
START and STOP bits. The I
2
C bus is considered to be busy
after START condition and free after STOP condition. During
data transmission, the I
2
C master can generate repeated
START conditions. First START and repeated START condi-
tions are equivalent, function-wise.
20129310
FIGURE 5. I
2
C Signals: Data Validity
L
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