參數(shù)資料
型號(hào): LP3927
廠商: National Semiconductor Corporation
英文描述: Cellular/PCS System Power Management IC
中文描述: 蜂窩/ PCS系統(tǒng)的電源管理IC
文件頁(yè)數(shù): 10/16頁(yè)
文件大小: 326K
代理商: LP3927
Keyboard Start-Up/Shut-Down
20037925
Note:
Diagram indicates Open Drain IRQ tied to V
DD
.
***
= Internal signal
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Delay between RST high-low transition to LDO2 disable.
11. Delay between LDO2 disable and LDO1 disable.
Keyboard de-bounce delay, 32 msec typ.
Delay between LDO1 reaching 95% of its output voltage and LDO2 enable, 125 μsec typical.
Both LDO1 and LDO2 outputs reach 95% of respective output voltage, start RST timer.
RST delay, 20 msec typical.
IRQ is active low.
Keyboard press must be greater than 32 msec.
PS_HOLD timer begins upon RST going high.
Maximum of 500 msec period from RST going high to PS_HOLD going high.
Response time from PS_HOLD going low to RST going low.
L
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