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參數(shù)資料
| 型號： | LP3923TL-VB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PBGA30 |
| 封裝： | 3 X 2.50 MM, MICRO SMD-30 |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 1718K |
| 代理商： | LP3923TL-VB |
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”ACKNOWLEDGE AFTER EVERY BYTE” RULE
The master generates an acknowledge clock pulse after each
byte transfer. The receiver sends an acknowledge signal after
every byte received.
There is one exception to the “acknowledge after every byte”
rule.
When the master is the receiver, it must indicate to the trans-
mitter an end of data by not-acknowledging (“negative ac-
knowledge”) the last byte clocked out of the slave. This
“negative acknowledge” still includes the acknowledge clock
pulse (generated by the master), but the SDA line is not pulled
down.
ADDRESSING TRANSFER FORMATS
Each device on the bus has a unique slave address. The
LP3923 operates as a slave device with the address 7h’7E
(binary nnnnnnnn). Before any data is transmitted, the master
transmits the address of the slave being addressed. The slave
device should send an acknowledge signal on the SDA line,
once it recognizes its address.
The slave address is the first seven bits after a Start Condi-
tion. The direction of the data transfer (R/W) depends on the
bit sent after the slave address — the eighth bit.
When the slave address is sent, each device in the system
compares this slave address with its own. If there is a match,
the device considers itself addressed and sends an acknowl-
edge signal. Depending upon the state of the R/W bit (1:read,
0:write), the device acts as a transmitter or a receiver.
CONTROL REGISTER WRITE CYCLE
Master device generates start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = '0').
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the addressed
register.
Slave sends acknowledge signal.
If master will send further data bytes the control register
address will be incremented by one after acknowledge
signal.
Write cycle ends when the master creates stop condition.
CONTROL REGISTER READ CYCLE
Master device generates a start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = '0').
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data
direction bit (r/w = “1”).
Slave sends acknowledge signal if the slave address is
correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control
register address will be incremented by one. Slave device
sends data byte from addressed register.
Read cycle ends when the master does not generate
acknowledge signal after data byte and generates stop
condition.
Address Mode
Data Read
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Data]<Ack or NAck>
… additional reads from subsequent register
address possible
<Stop Condition>
Data Write
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register
address possible
<Stop Condition>
< > Data from master [ ] Data from slave
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LP3923
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LP3923TL-VB/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3923TL-VC | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Cellular Phone Power Management Unit |
| LP3923TL-VC/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
| LP3923TL-VI | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Cellular Phone Power Management Unit |
| LP3923TL-VI/NOPB | 功能描述:PMIC 解決方案 RoHS:否 制造商:Texas Instruments 安裝風格:SMD/SMT 封裝 / 箱體:QFN-24 封裝:Reel |
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