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參數(shù)資料
| 型號： | LP2987AIM-2.8 |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Circular Connector; No. of Contacts:79; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:20-35 RoHS Compliant: No |
| 中文描述： | 2.8 V FIXED POSITIVE LDO REGULATOR, 0.35 V DROPOUT, PDSO8 |
| 封裝： | SO-8 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大小： | 513K |
| 代理商： | LP2987AIM-2.8 |
Application Hints
(Continued)
The external capacitor c
sets the delay time (T
).
The value of capacitor required for a given time delay may
be calculated using the formula:
C
DLY
= T
DELAY
/(5.59 X 10
5
)
To simplify design, a plot is provided below which shows val-
ues of C
DLY
versus delay time.
DETAILS OF ERR/RESET CIRCUIT OPERATION:
(Refer
to LP2987/8 Equivalent Circuit).
The output of comparator U2 is the ERR/RESET flag. Since
it is an open-collector output, it requires the use of a pull-up
resistor (R
). The 1.23V reference is tied to the inverting in-
put of U2, which means that its output is controlled by the
voltage applied to the non-inverting input.
The output of U1 (also an open-collector) will force the non-
inverting input of U2 to go low whenever the LP2987/8 regu-
lated output drops about 5% below nominal.
U1’s inverting input is also held at 1.23V. The other input
samples the regulated output through a resistive divider (R
A
and R
). When the regulated output is at nominal voltage,
the voltage at the divider tap point will be 1.23V. If this volt-
age drops about 60 mV below 1.23V, the output of U1 will go
low forcing the output of U2 low (which is the ERROR state).
Power-ON reset delay occurs when a capacitor (shown as
C
) is connected to the Delay pin. At turn-ON, this capaci-
tor is initially fully discharged (which means the voltage at
the Delay pin is 0V). The output of U1 keeps C
fully dis-
charged (by sinking the 2.2 μA from the current source) until
the regulator output voltage comes up to within about 5% of
nominal. At this point, U1’s output stops sinking current and
the 2.2 μA starts charging up C
DLY
.
When the voltage across C
reaches 1.23V, the output of
U2 will go high (note that D1 limits the maximum voltage to
about 2V).
SELECTING C
: The maximum recommended value for
this capacitor is 1 μF. The capacitor must not have exces-
sively high leakage current, since it is being charged from a
2.2 μA current source.
Aluminum electrolytics can not be used, but good-quality
tantalum, ceremic, mica, or film types will work.
SHUTDOWN INPUT OPERATION
The LP2987/8 is shut off by driving the Shutdown input low,
and turned on by pulling it high. If this feature is not to be
used, the Shutdown input should be tied to V
IN
to keep the
regulator output on at all times.
DS100017-9
Timing Diagram for Power-Up
DS100017-11
Plot of C
DLY
vs T
DELAY
DS100017-10
LP2987/8 Equivalent Circuit
www.national.com
16
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| LP2987AIM-3.0/NOPB | 功能描述:IC REG LDO 3V .2A 8-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式 輸出電壓:4V 輸入電壓:最高 16V 電壓 - 壓降（標(biāo)準(zhǔn)）:0.28V @ 150mA 穩(wěn)壓器數(shù)量:1 電流 - 輸出:150mA 電流 - 限制（最?。?- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:5-VFBGA 供應(yīng)商設(shè)備封裝:5-uSMD 包裝:Digi-Reel® 其它名稱:LP2985AIBP-4.0DKR |
| LP2987AIM-3.2/NOPB | 功能描述:IC REG LDO 3.2V .2A 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式 輸出電壓:4V 輸入電壓:最高 16V 電壓 - 壓降（標(biāo)準(zhǔn)）:0.28V @ 150mA 穩(wěn)壓器數(shù)量:1 電流 - 輸出:150mA 電流 - 限制（最小）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:5-VFBGA 供應(yīng)商設(shè)備封裝:5-uSMD 包裝:Digi-Reel® 其它名稱:LP2985AIBP-4.0DKR |
| LP2987AIM-3.3/NOPB | 功能描述:IC REG LDO 3.3V .2A 8-SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - 線性 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):正，固定式 輸出電壓:4V 輸入電壓:最高 16V 電壓 - 壓降（標(biāo)準(zhǔn)）:0.28V @ 150mA 穩(wěn)壓器數(shù)量:1 電流 - 輸出:150mA 電流 - 限制（最?。?- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:5-VFBGA 供應(yīng)商設(shè)備封裝:5-uSMD 包裝:Digi-Reel® 其它名稱:LP2985AIBP-4.0DKR |
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