參數(shù)資料
型號(hào)： LP2975AIMM-12/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PDSO8
封裝： MINI, SOP-8
文件頁(yè)數(shù)： 4/20頁(yè)
文件大?。?/td> 1135K
代理商： LP2975AIMM-12/NOPB
Application Hints (Continued)
1) The Gate pin of the LP2975 (which drives the Gate of the
FET) has a limited amount of current to source or sink. This
means faster changes in Gate voltage (which corresponds to
faster transient response) will occur with a smaller amount of
Gate capacitance.
2) The Gate capacitance forms a pole in the loop gain which
can reduce phase margin. When possible, this pole should
be kept at a higher frequency than the cross-over frequency
of the regulator loop (see later section CROSS-OVER FRE-
QUENCY AND PHASE MARGIN).
A high value of Gate capacitance may require that a feed-
forward capacitor be used to cancel some of the excess
phase shift (see later section FEED-FORWARD CAPACI-
TOR) to prevent loop instability.
POWER DISSIPATION: The maximum power dissipated in
the FET in any application can be calculated from:
P
MAX =(VIN VOUT)xIMAX
Where the term I
MAX is the maximum output current. It
should be noted that if the regulator is to be designed to
withstand short-circuit, a current sense resistor must be
used to limit I
MAX to a safe value (refer to section SHORT-
CIRCUIT CURRENT LIMITING).
The power dissipated in the FET determines the best choice
for package type. A TO-220 package device is best suited for
applications where power dissipation is less than 15W.
Power levels above 15W would almost certainly require a
TO-3 type device.
In low power applications, surface-mount package devices
are size-efficient and cost-effective, but care must be taken
to not exceed their power dissipation limits.
POWER DISSIPATION AND HEATSINKING
Since the LP2975 controller is suitable for use with almost
any external P-FET, it follows that designs can be built which
have very high power dissipation in the pass FET. Since the
controller can not protect the FET from overtemperature
damage, thermal design must be carefully done to assure a
reliable design.
THERMAL DESIGN METHOD: The temperature of the FET
and the power dissipated is defined by the equation:
T
J =(
θ
J-A xPD)+ TA
Where:
T
J is the junction temperature of the FET.
T
A is the ambient temperature.
P
D is the power dissipated by the FET.
θ
J-A is the junction-to-ambient thermal resistance.
To ensure a reliable design, the following guidelines are
recommended:
1) Design for a maximum (worst-case) FET junction tem-
perature which does not exceed 150C.
2) Heatsinking should be designed for worst-case (maxi-
mum) values of T
A and PD.
3) In designs which must survive a short circuit on the output,
the maximum power dissipation must be calculated assum-
ing that the output is shorted to ground:
P
D(MAX) = VIN xISC
Where I
SC is the short-circuit output current.
4) If the design is not intended to be short-circuit proof, the
maximum power dissipation for intended operation will be:
P
D(MAX) = (VIN VOUT)xIMAX
Where I
MAX is the maximum output current.
LOW POWER (<2W) APPLICATIONS: In most cases,
some type of small surface-mount device will be used for the
FET in low power designs. Because of the increased cell
density (and tiny packages) used by modern FET’s, the
current carrying capability may easily exceed the power
dissipation limits of the package. It is possible to parallel two
or more FET’s, which divides the power dissipation among
all of the packages.
It should be noted that the “heatsink” for a surface mount
package is the copper of the PC board and the package itself
(direct radiation).
Surface-mount devices have the value of
θ
J-A specified for a
typical PC board mounting on their data sheet. In most cases
it is best to start with the known data for the application (P
D,
T
A,TJ) and calculate the required value of
θ
J-A needed. This
value will define the type of FET and, possibly, the heatsink
required for cooling.
θ
J-A =(TJ TA)/PD(MAX)
DESIGN EXAMPLE: A design is to be done with V
IN =5V
and V
OUT = 3.3V with a maximum load current of 300 mA.
Based on these conditions, power dissipation in the FET
during normal operation would be:
P
D =(VIN VOUT)xILOAD
Solving, we find that P
D = 0.51W. Assuming that the maxi-
mum allowable value of T
J is 150C and the maximum TA is
70C, the value of
θ
J-A is found to be 157C/W.
However, if this design must survive a continuous short on
the output, the power dissipated in the FET is higher:
P
D(SC) = VIN xISC = 5 x 0.33 = 1.65W
(This assumes the current sense resistor is selected for an
I
SC value that is 10% higher than the required 0.3A).
The value of
θ
J-A required to survive continuous short circuit
is calculated to be 49C/W.
Having solved for the value(s) of
θ
J-A, a FET can be se-
lected. It should be noted that a FET must be used with a
θ
J-A value less than or equal to the calculated value.
HIGH POWER (
≥2W) APPLICATIONS: As power dissipa-
tion increases above 2W, a FET in a larger package must be
used to obtain lower values of
θ
J-A. The same formulae
derived in the previous section are used to calculate P
D and
θ
J-A.
Having found
θ
J-A, it becomes necessary to calculate the
value of
θ
S-A (the heatsink-to-ambient thermal resistance) so
that a heatsink can be selected:
θ
S-A =
θ
J-A (
θ
J-C +
θ
C-S)
Where:
θ
J-C is the junction-to-case thermal resistance. This pa-
rameter is the measure of thermal resistance between the
semiconductor die inside the FET and the surface of the
case of the FET where it mounts to the heatsink (the value of
θ
J-C can be found on the data sheet for the FET). A typical
FET in a TO-220 package will have a
θ
J-C value of approxi-
mately 2–4C/W, while a device in a TO-3 package will be
about 0.5–2C/W.
θ
C-S is the case-to-heatsink thermal resistance, which
measures how much thermal resistance exists between the
surface of the FET and the heatsink.
θ
C-S is dependent on
the package type and mounting method. A TO-220 package
with mica insulator and thermal grease secured to a heatsink
will have a
θ
C-S value in the range of 1–1.5C/W. A TO-3
package mounted in the same manner will have a
θ
C-S value
LP2975
www.national.com
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