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參數(shù)資料
| 型號： | LP064V1 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | LP064V1 LIQUID CRYSTAL DISPLAY |
| 中文描述： | LP064V1液晶顯示器 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 249K |
| 代理商： | LP064V1 |
LP064V1 LIQUID CRYSTAL DISPLAY
SPECIFICATIONS
TITLE: LP064V1 REV. 1 PAGE 7
OF 7
DATA DISPLAY AG
Industriestrasse 1
D-82110 Germering
MAY 2001
http://www.datadisplay.de
Tel.: +49-89-894450-0
Fax: +49-89-894450-90
5.
INTERFACE CONNECTIONS
This LCD employs two interface connections, a 31 pin connector is used for the
module and a three pin connector is used for the integral backlight system. The
electric interface connector is model DF9B-31P-1V, manufactured by Hirose. The
mating connector part number is DF9-31S-1V or equivalent. The pin configuration
for the connector is shown in the table below.
Table 3: MODULE CONNECTOR PIN CONFIGURATION
Pin
Symbol
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
NC
No Connection
Notes
Vss
CLK
Hsync
Vsync
Vss
R0
R1
R2
R3
R4
R5
Vss
G0
G1
G2
G3
G4
G5
Vss
B0
B1
B2
B3
B4
B5
Vss
DTMG
Vdd
Vdd
OAS
Ground
Main clock
Horizontal sync.
Vertical sync.
Ground
Red data
Red data
Red data
Red data
Red data
Red data
Ground
Green data
Green data
Green data
Green data
Green data
Green data
Ground
Blue data
Blue data
Blue data
Blue data
Blue data
Blue data
Ground
Data Timing Signal
Power(+5V)
Power(+5V)
O/A, A/V Selection
Connect to Vss, see Note 1
Connect to Vss, see Note 1
Red data least significant bit(LSB)
Red data most significant bit(MSB)
Connect to Vss, see Note 1
Green data least significant bit(LSB)
Green data most significant bit(MSB)
Connect to Vss, see Note 1
Blue data least significant bit(LSB)
Blue data most significant bit(MSB)
Connect to Vdd, see Note 2
Connect to Vdd, see Note 2
see Note3
Note 1: All GND (ground) pins should be connected together and to Vss which
should also be connected to the LCD’s metal frame.
Note 2: All V
DD
(power input) pins should be connected together.
Note 3: This pin is Logic input pin and is connected V
DD
(power input) with surge
protection circuit.
Note 4: DTMG, HSYNC and VSYNC shall be supplied simultaneously.
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