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參數(shù)資料
| 型號(hào)： | LNK626DG-TL |
| 廠商： | POWER INTEGRATIONS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PDSO7 |
| 封裝： | GREEN, PLASTIC, MS-012, SOP-8/7 |
| 文件頁(yè)數(shù)： | 18/18頁(yè) |
| 文件大?。?/td> | 535K |
| 代理商： | LNK626DG-TL |
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Rev. E 09/09
9
LNK623-626
www.powerint.com
Figure 11. Not Pulse Grouping (<5 Consecutive Switching Cycles).
Pulse Grouping (>5 Consecutive Switching Cycles).
Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)
Split Screen with Bottom Screen Zoom
Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)
Clampless Designs
Clampless designs rely solely on the drain node capacitance to
limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the value
of V
OR, the leakage inductance energy, (a function of leakage
inductance and peak primary current), and the primary winding
capacitance determine the peak drain voltage. With no signi-
cant dissipative element present, as is the case with an external
clamp, the longer duration of the leakage inductance ringing can
increase EMI.
The following requirements are recommended for a universal
input or 230 VAC only Clampless design:
1. Clampless designs should only be used for P
O ≤5 W using a
V
OR of ≤90 V
2. For designs with P
O ≤5 W, a two-layer primary must be used
to ensure adequate primary intra-winding capacitance in the
range of 25 pF to 50 pF. A bias winding must be added to
the transformer using a standard recovery rectier diode
(1N4003– 1N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting a
resistor from the bias winding capacitor to the BYPASS pin.
This inhibits the internal high-voltage current source,
reducing device dissipation and no-load consumption.
3. For designs with P
O >5 W, Clampless designs are not practical
and an external RCD or Zener clamp should be used.
4. Ensure that worst-case, high line, peak drain voltage is below
the BV
DSS specication of the internal MOSFET and ideally
≤650 V to allow margin for design variation.
V
OR (Reected Output Voltage), is the secondary output plus
output diode forward voltage drop that is reected to the primary
via the turns ratio of the transformer during the diode conduction
time. The V
OR adds to the DC bus voltage and the leakage spike
to determine the peak drain voltage.
Pulse Grouping
Pulse grouping is dened as 6 or more consecutive pulses
followed by two or more timing state changes. The effect of
pulse grouping is increased output voltage ripple. This is
shown on the right of Figure 11 where pulse grouping has
caused an increase in the output ripple.
To eliminate group pulsing verify that the feedback signal settles
within 2.1 μs from the turn off of the internal MOSFET. A Zener
diode in the clamp circuit may be needed to achieve the desired
settling time. If the settling time is satisfactory, then a RC
network across R
LOWER (R6) of the feedback resistors is
necessary.
The value of R (R5 in the Figure 12) should be an order of
magnitude greater than R
LOWER
and selected such that
R×C = 32 μs where C is C5 in Figure 12.
Quick Design Checklist
As with any power supply design, all LinkSwitch-CV designs
should be veried on the bench to make sure that component
specications are not exceeded under worst-case conditions.
Figure 12. RC Network Across R
BOTTOM (R6) to Reduce Pulse Grouping.
PI-5268-110608
D
S
FB
BP
R3
6.34 k
1%
R6
4.02 k
1%
R4
6.2 k
C4
1 F
50 V
C5
680 pF
50 V
C6
10 F
50 V
R5
47 k
1/8 W
U1
LNK626PG
LinkSwitch-CV
D6
1N4148
5
4
2
Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)
Split Screen with Bottom Screen Zoom
Top Trace: Drain Waveform (200 V/div)
Bottom Trace: Output Ripple Voltage (50 mV/div)
相關(guān)PDF資料 |
PDF描述 |
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| LNK625PG-TL | SPECIALTY ANALOG CIRCUIT, PDIP7 |
| LNK626DG | SPECIALTY ANALOG CIRCUIT, PDSO7 |
| LOG102AIDRG4 | LOG OR ANTILOG AMPLIFIER, 1.4 MHz BAND WIDTH, PDSO14 |
| LOG102AIDR | LOG OR ANTILOG AMPLIFIER, 1.4 MHz BAND WIDTH, PDSO14 |
| LOG102AIDG4 | LOG OR ANTILOG AMPLIFIER, 1.4 MHz BAND WIDTH, PDSO14 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LNK626PG | 功能描述:交流/直流開關(guān)轉(zhuǎn)換器 8.5 W (85-265 VAC) RoHS:否 制造商:STMicroelectronics 輸出電壓:800 V 輸入/電源電壓（最大值）:23.5 V 輸入/電源電壓（最小值）:11.5 V 開關(guān)頻率:115 kHz 電源電流:1.6 mA 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SSO-10 封裝:Reel |
| LNK632DG | 功能描述:交流/直流開關(guān)轉(zhuǎn)換器 3.1 W (85-265 VAC) RoHS:否 制造商:STMicroelectronics 輸出電壓:800 V 輸入/電源電壓（最大值）:23.5 V 輸入/電源電壓（最小值）:11.5 V 開關(guān)頻率:115 kHz 電源電流:1.6 mA 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SSO-10 封裝:Reel |
| LNK632DG-TL | 功能描述:交流/直流開關(guān)轉(zhuǎn)換器 3.1 W (85-265 VAC) RoHS:否 制造商:STMicroelectronics 輸出電壓:800 V 輸入/電源電壓（最大值）:23.5 V 輸入/電源電壓（最小值）:11.5 V 開關(guān)頻率:115 kHz 電源電流:1.6 mA 工作溫度范圍:- 40 C to + 150 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SSO-10 封裝:Reel |
| LNK6663E | 功能描述:初級(jí)與次級(jí)側(cè) PWM 控制器 Off-Line Switcher PSR, LinkSwitch - HP RoHS:否 制造商:ON Semiconductor 輸出端數(shù)量:1 開關(guān)頻率:250 KHz 工作電源電壓:- 0.3 V to + 28 V 最大工作溫度:+ 85 C 最小工作溫度:- 5 C 封裝 / 箱體:SOIC-8 Narrow 封裝:Reel |
| LNK6663V | 功能描述:初級(jí)與次級(jí)側(cè) PWM 控制器 Off-Line Switcher IC PSR LinkSwitch HP RoHS:否 制造商:ON Semiconductor 輸出端數(shù)量:1 開關(guān)頻率:250 KHz 工作電源電壓:- 0.3 V to + 28 V 最大工作溫度:+ 85 C 最小工作溫度:- 5 C 封裝 / 箱體:SOIC-8 Narrow 封裝:Reel |
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