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參數(shù)資料
| 型號： | LMZ3020-7ERD5AF |
| 廠商： | POWER-ONE INC |
| 元件分類： | 電源模塊 |
| 英文描述： | 3-OUTPUT 50 W AC-DC REG PWR SUPPLY MODULE |
| 封裝： | METAL, CASE M02, MODULE |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 982K |
| 代理商： | LMZ3020-7ERD5AF |
Cassette Style
AC-DC Converters
M Series
Edition 5/5.2000
20/24
D Undervoltage Monitor
The input and/or output undervoltage monitoring circuit op-
erates independently of the built-in input undervoltage lock-
out circuit. A logic "low" (JFET output) or "high" signal (NPN
output) is generated at pin 5 as soon as one of the moni-
tored voltages drops below the preselected threshold level
Ut. The return for this signal is Vo1– (pin 23). The D output
recovers when the monitored voltage(s) exceed(s)
Ut+Uh.
Table 22: Undervoltage monitor functions
Output type
Monitoring
Minimum adjustment range
Typical hysteresis
Uh for
JFET
NPN
Ui
Uo1
of threshold level
Ut
Ut min...Ut max [% of Ut]
Uti
Uto
Uhi
Uho
D1
D5
no
yes
–
3.5 V...48 V 1
–
2.3...1
D2
D6
yes
no
Ui min...Ui max 1
–
3.0...0.5
–
D3
D7
yes
Ui min...Ui max 1
0.95...0.98
Uo1 2
3.0...0.5
"0"
D4
D8
no
yes
–
0.95...0.98
Uo1 2
–
"0"
D0
D9
no
yes
–
3.5 V...48 V 3
–
1.8...1
yes
no
Ui min...Ui max 3 4
–
2.2...0.4
–
yes
Ui min...Ui max 3 4
0.95...0.98
Uo1 2
2.2...0.4
"0"
1 Threshold level adjustable by potentiometer (not recommended for mobile applications)
2 Fixed value between 95% and 98% of Uo1 (tracking)
3 Fixed value, resistor-adjusted according to customer's specifications
±2% at 25°C; individual type number is determined by Power-
One
4 Adjusted at Io nom
JFET output (D0…D4):
Connector pin D is internally connected via the drain-
source path of a JFET (self-conducting type) to the nega-
tive potential of output 1.
UD
≤ 0.4 V (logic low) corresponds
to a monitored voltage level (
Ui and/or Uo1)
< U
t. The cur-
rent
ID through the JFET should not exceed 2.5 mA. The
JFET is protected by a 0.5 W Zener diode of 8.2 V against
external overvoltages.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
low, L,
UD ≤ 0.4 V at ID = 2.5 mA
Ui and Uo1 > Ut + Uh
high, H,
ID ≤ 25 A at UD = 5.25 V
Fig. 24
Options D0...D4, JFET output
Vo1+
Vo1–
D
UD
ID
Rp
Input
11006
NPN output (D5...D9):
Connector pin D is internally connected via the collector-
emitter path of a NPN transistor to the negative potential of
output 1.
UD
≤ 0.4 V (logic low) corresponds to a monitored
voltage level (
Ui and/or Uo1)
> U
t + Uh. The current ID
through the open collector should not exceed 20 mA. The
NPN output is not protected against external overvoltages.
UD should not exceed 40 V.
Ui, Uo1 status
D output,
UD
Ui or Uo1 < Ut
high, H,
ID ≤ 25 A at UD = 40 V
Ui and Uo1 > Ut + Uh
low, L,
UD ≤ 0.4 V at ID = 20 mA
Vo1+
Vo1–
D
UD
ID
Rp
Input
11007
Fig. 25
Options D5...D9, NPN output
The threshold level
Ut is either adjustable by a potentio-
meter, accessible through a hole in the front cover, or is fac-
tory adjusted to a fixed value specified by the customer.
Option D exists in various versions D0...D9 as shown in the
following table.
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