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| 型號(hào)： | LMZ14202EXTTZ-ADJ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING REGULATOR, PSSO7 |
| 封裝： | 10.16 X 13.77 MM, 4.57 MM HEIGHT, ROHS COMPLIANT, TO-PMOD-7 |
| 文件頁(yè)數(shù)： | 5/18頁(yè) |
| 文件大小： | 3941K |
| 代理商： | LMZ14202EXTTZ-ADJ |
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I
DCBVO*(VIN–VO)/(2*10 μH*fSW(CCM)*VIN) (16)
Following is a typical waveform showing the boundary condi-
tion.
Transition Mode Operation
V
IN = 24V, VO = 3.3V, IO = 0.35A 2 μsec/div
30117714
The inductor internal to the module is 10
μH. This value was
chosen as a good balance between low and high input voltage
applications. The main parameter affected by the inductor is
the amplitude of the inductor ripple current (I
LR). ILR can be
calculated with:
I
LR P-P=VO*(VIN- VO)/(10H*fSW*VIN) (17)
Where V
IN is the maximum input voltage and fSW is deter-
mined from equation 10.
If the output current I
O is determined by assuming that IO =
I
L, the higher and lower peak of ILR can be determined. Be
aware that the lower peak of I
LR must be positive if CCM op-
eration is required.
POWER DISSIPATION AND BOARD THERMAL
REQUIREMENTS
For the design case of V
IN = 24V, VO = 3.3V, IO = 2A, TAMB
(MAX) = 85°C , and TJUNCTION = 125°C, the device must see a
thermal resistance from case to ambient of:
θ
CA< (TJ-MAX — TAMB(MAX)) / PIC-LOSS - θJC (18)
Given the typical thermal resistance from junction to case to
be 1.9 °C/W. Use the 85°C power dissipation curves in the
Typical Performance Characteristics section to estimate the
P
IC-LOSS for the application being designed. In this application
it is 1.5W.
θ
CA = (125 — 85) / 1.5W — 1.9) = 24.8
To reach
θ
CA = 24.8, the PCB is required to dissipate heat
effectively. With no airflow and no external heat, a good esti-
mate of the required board area covered by 1 oz. copper on
both the top and bottom metal layers is:
Board Area_cm2 = 500°C x cm2/W /
θ
JC (19)
As a result, approximately 20.2 square cm of 1 oz copper on
top and bottom layers is required for the PCB design. The
PCB copper heat sink must be connected to the exposed pad.
Approximately thirty six, 10mils (254
μm) thermal vias spaced
59mils (1.5 mm) apart must connect the top copper to the
bottom copper. For an example of a high thermal performance
PCB layout, refer to the Evaluation Board application note
AN-2024.
PC BOARD LAYOUT GUIDELINES
PC board layout is an important part of DC-DC converter de-
sign. Poor board layout can disrupt the performance of a DC-
DC converter and surrounding circuitry by contributing to EMI,
ground bounce and resistive voltage drop in the traces. These
can send erroneous signals to the DC-DC converter resulting
in poor regulation or instability. Good layout can be imple-
mented by following a few simple design rules.
30117711
1. Minimize area of switched current loops.
From an EMI reduction standpoint, it is imperative to minimize
the high di/dt paths during PC board layout. The high current
loops that do not overlap have high di/dt content that will
cause observable high frequency noise on the output pin if
the input capacitor (Cin1) is placed at a distance away from
the LMZ14202EXT. Therefore place C
IN1 as close as possible
to the LMZ14202EXT VIN and GND exposed pad. This will
minimize the high di/dt area and reduce radiated EMI. Addi-
tionally, grounding for both the input and output capacitor
should consist of a localized top side plane that connects to
the GND exposed pad (EP).
2. Have a single point ground.
The ground connections for the feedback, soft-start, and en-
able components should be routed to the GND pin of the
device. This prevents any switched or load currents from
flowing in the analog ground traces. If not properly handled,
poor grounding can result in degraded load regulation or er-
ratic output voltage ripple behavior. Provide the single point
ground connection from pin 4 to EP.
3. Minimize trace length to the FB pin.
Both feedback resistors, R
FBT and RFBB, and the feed forward
capacitor C
FF, should be located close to the FB pin. Since
the FB node is high impedance, maintain the copper area as
small as possible. The trace are from R
FBT, RFBB, and CFF
should be routed away from the body of the LMZ14202EXT
to minimize noise.
4. Make input and output bus connections as wide as
possible.
This reduces any voltage drops on the input or output of the
converter and maximizes efficiency. To optimize voltage ac-
curacy at the load, ensure that a separate feedback voltage
sense trace is made to the load. Doing so will correct for volt-
age drops and provide optimum output accuracy.
5. Provide adequate device heat-sinking.
Use an array of heat-sinking vias to connect the exposed pad
to the ground plane on the bottom PCB layer. If the PCB has
a plurality of copper layers, these thermal vias can also be
employed to make connection to inner layer heat-spreading
ground planes. For best results use a 6 x 6 via array with
minimum via diameter of 10mils (254
μm) thermal vias spaced
59mils (1.5 mm). Ensure enough copper area is used for heat-
sinking to keep the junction temperature below 125°C.
13
www.national.com
LMZ14202EXT
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相關(guān)代理商/技術(shù)參數(shù) |
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| LMZ14202EXTTZE | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2A SIMPLE SWITCHER?? Power Module with 42V Maximum Input Voltage for Military and Rugged Applications |
| LMZ14202EXTTZE/NOPB | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT |
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| LMZ14202EXTTZX | 制造商:TI 制造商全稱:Texas Instruments 功能描述:2A SIMPLE SWITCHER?? Power Module with 42V Maximum Input Voltage for Military and Rugged Applications |
| LMZ14202EXTTZX/NOPB | 功能描述:直流/直流開關(guān)轉(zhuǎn)換器 RoHS:否 制造商:STMicroelectronics 最大輸入電壓:4.5 V 開關(guān)頻率:1.5 MHz 輸出電壓:4.6 V 輸出電流:250 mA 輸出端數(shù)量:2 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT |
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