參數(shù)資料
型號(hào): LMX3161VBHX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 無繩電話/電話
英文描述: Single Chip Radio Transceiver
中文描述: TELECOM, CORDLESS, SUPPORT CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, QFP-48
文件頁數(shù): 8/14頁
文件大小: 212K
代理商: LMX3161VBHX
PLL Functional Description
The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit
data register, 18-bit F-latch, 12-bit N-counter, and 6-bit R-counter.
The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control
bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred
to the addressed register accordingly. The decoding scheme of the two control bits is as follows:
Control Bits
Register
C2
0
1
X
C1
0
0
1
N-Counter
R-Counter
F-Latch
Note:
X = Don’t Care Condition
Programmable Feedback Divider (N-Counter)
The N-counter consists of the 6-bit swallow counter (A-counter) and the 6-bit programmable counter (B-counter). When the con-
trol bits are “00”, data is transferred from the 20-bit shift register into two 6-bit latches. One latch sets theA-counter while the other
sets the B-counter. The serial data format is shown below.
MSB
19
REGISTER’S BIT MAPPING
11
10
N-COUNTER’s Divide Ratio
N11
N10
N9
N8
LSB
18
17
16
15
14
13
12
9
8
7
6
5
4
3
2
1
0
RESERVED
X
C2
0
C1
0
X
X
X
X
X
N12
N7
N6
N5
N4
N3
N2
N1
Note:
X = Don’t Care Condition
Swallow Counter Divide Ratio (A-Counter)
Divide Ratio, A
0
1
*
63
N6
0
0
*
1
N5
0
0
*
1
N4
0
0
*
1
N3
0
0
*
1
N2
0
0
*
1
N1
0
1
*
1
Note:
Divide ratio must be from 0 to 63, and B must be
A.
Programmable Counter Divide Ratio (B-Counter)
Divide Ratio, B
3
4
*
63
N12
0
0
*
1
N11
0
0
*
1
N10
0
0
*
1
N9
0
1
*
1
N8
1
0
*
1
N7
1
0
*
1
Note:
Divide ratio must be from 3 to 63, and B must be
A.
DS012815-4
L
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8
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