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參數(shù)資料
| 型號： | LMX2542 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO |
| 中文描述： | PLLatinum蜂窩頻率合成器和GPS系統(tǒng)的集成VCO |
| 文件頁數(shù)： | 18/22頁 |
| 文件大?。?/td> | 253K |
| 代理商： | LMX2542 |
2.0 Programming Description
(Continued)
2.3 R1 REGISTER
The R1 register contains the FREQ_OFF, RF_EN and OB_CRL control words. The register address bits are R1[1:0] = 01. The
detailed descriptions and programming information for each control word is discussed in the following sections.
Reg
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MSB
SHIFT REGISTER BIT LOCATION
LSB
DATA[21:0]
ADDRESS
[1:0]
FIELD
R1
0
1
1
0
1
0
0
0
1
0
1
0
1
0
1
0
0
1
OB_CRL
[1:0]
RF_
EN
FREQ_
OFF
0
1
2.3.1 FREQ_OFF - RF Synthesizer System Frequency Offset (R1[2])
The FREQ_OFF bit is used to offset the RF frequency by +5 kHz.
Control Bit
Register Location
Description
Function
0
1
FREQ_OFF
R1[2]
RF Synthesizer
System Frequency
Offset
RF Synthesizer
System Frequency
Offset Disabled
RF Synthesizer
System Frequency
Offset Enabled
2.3.2 RF_EN - RF Synthesizer System Enable (R1[3])
The RF_EN bit is used to switch the RF synthesizer system (PLL and VCO) between a powered up and powered down mode.
Control Bit
Register Location
Description
Function
0
1
RF_EN
R1[3]
RF Synthesizer
System Enable
RF Synthesizer
System Powered
Down
RF Synthesizer
System Active
2.3.3 OB_CRL[1:0] - RF VCO Output Buffer Power Control (R1[5:4])
The OB_CRL word is used to set the RF VCO output buffer power level. The power level can be set according to the system
requirements.
OB_CRL[1:0]
RF VCO Output Buffer Power Level
(dBm)
4.5
2.0
0.5
3.0
0
0
1
1
0
1
0
1
L
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