參數(shù)資料
型號(hào)： LMX2532LQX1065
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： PLLatinum Frequency Synthesizer System with Integrated VCOs
中文描述： PLL FREQUENCY SYNTHESIZER, 19.68 MHz, QCC28
封裝： 5 X 5 MM, 0.75 MM HEIGHT, LLP-28
文件頁數(shù)： 13/18頁
文件大?。?/td> 189K
代理商： LMX2532LQX1065
Programming Description
(Continued)
R1 REGISTER
The R1 register address bits (R1 [1:0]) are “01”.
The IF_FREQ bits selects the default IF frequency applicable to the specific CDMA system. For the LMX2522 the default IF
frequency is 440.76 MHz, and for the LMX2532 the default IF frequencies are 367.20 MHz and 170.76 MHz, depending on
variant.
Reference Frequency Selection bit (OSC_FREQ) selects either 19.20 MHz or 19.68 MHz for the reference oscillator frequency.
The internal spurious reduction scheme is controlled by the SPUR_RDT [1:0] bits. There are two different spur reduction
schemes: a continuous tracking mode and a single optimization mode. The continuous tracking mode will adjust for variations in
voltage and temperature. The single optimization mode fixes the internal compensation parameters only when the PLL goes into
the locked state. The spur reduction can also be disabled, but it is recommended that the continuous mode be used for normal
operation.
The OB_CRL [1:0] bits determine the power level of the RF output buffer. The power level is set according to the system
requirement.
The two bits, RF_EN and IF_EN, logically select the active state of the RF/GPS synthesizer system and the IF PLL, respectively.
The entire IC can be placed in a power down state by using the CE control pin (pin 20).
R1 REGISTER
R
MSB
23
SHIFT REGISTER BIT LOCATION
16
15
14
13
Data Field
LSB
0
22
21
20
19
18
17
12
11
10
9
8
7
6
5
4
3
2
1
Address
Field
0
1
R1
(Default)
IF_
FREQ
[1:0]
OSC_
FREQ
1
0
0
0
0
0
0
0
SPUR_
RDT
[1:0]
0
0
1
0
1
OB_
CRL
[1:0]
RF_
EN
IF_
EN
Name
IF_FREQ [1:0]
Functions
IF Frequency Selection
00 = 170.76 MHz (LMX2532LQ0967)
01 = 367.20 MHz (LMX2532LQ1065)
10 = 440.76 MHz (LMX2522LQ1635)
Reference Frequency Selection
0 = 19.20 MHz
1 = 19.68 MHz
Spur Reduction Scheme
00 = No spur reduction
01 = Not Used
10 = Continuous tracking of variation (Recommended)
11 = One time optimization
RF Output Power Control
00 = Minimum Output Power
01 =
10 =
11 = Maximum Output Power
RF Enable
0 = RF Off
1 = RF On
IF Enable
0 = IF Off
1 = IF On
OSC_FREQ
SPUR_RDT [1:0]
OB_CRL [1:0]
RF_EN
IF_EN
L
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相關(guān)PDF資料
PDF描述
LMX2532LQ0967 PLLatinum Frequency Synthesizer System with Integrated VCOs
LMX2532 PLLatinum Frequency Synthesizer System with Integrated VCOs
LMX2542LQ2121 PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO
LMX2542LQX2121 PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO
LMX2542 PLLatinum Cellular and GPS Frequency Synthesizer System with Integrated VCO
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