參數(shù)資料
型號(hào): LMX2525LQX1321
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: PLLatinum Dual Frequency Synthesizer System with Integrated VCOs
中文描述: PLL FREQUENCY SYNTHESIZER, 26 MHz, QCC24
封裝: 5 X 4 MM, 0.75 MM HEIGHT, LLP-24
文件頁數(shù): 12/17頁
文件大?。?/td> 237K
代理商: LMX2525LQX1321
Programming Description
GENERAL PROGRAMMING INFORMATION
The serial interface has a 24-bit shift register to store the incoming data bits temporarily. The incoming data is first loaded into the
shift register from MSB to LSB. The data is shifted at the rising edge of the clock signal. When the latch enable signal transitions
from LOW to HIGH, the data stored in shift register is transferred to the proper register depending on the address bit setting. The
selection of the particular register is determined by the control bits indicated in boldface text.
At initial start-up, the MICROWIRE loading requires three default words (registers R2, loaded first, to R0, loaded last). After the
device has been initially programmed, the RF VCO frequency can be changed using a single register (R0).
The control register content map describes how the bits within each control register are allocated to the specific control functions.
COMPLETE REGISTER MAP
R
MSB
SHIFT REGISTER BIT LOCATION
LSB
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R0
(Default)
R1
(Default)
RX/
TX
SPI_
DEF
RF_
PD
0
HS
0
BS
RF_B
[3:0]
1
RF_A
[2:0]
0
RF_FN
[9:0]
0
LD
0
0
0
1
0
0
0
1
0
0
0
0
0
1
OB_
CRL
[1:0]
0
OSC_
FREQ
[1:0]
0
0
1
R2
(Default)
R3
R4
R5
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
0
1
1
1
1
1
1
1
1
Note:
R0 control register will be used when hot start frequency change.
Note: Boldface
text represent address bits.
L
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