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參數(shù)資料
| 型號： | LMX2487ESQ |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 7500 MHz, PQCC24 |
| 封裝： | 4 X 4 MM, 0.80 MM HEIGHT, LLP-24 |
| 文件頁數(shù)： | 32/38頁 |
| 文件大小： | 419K |
| 代理商： | LMX2487ESQ |
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2.5.5 OSC_OUT Oscillator Output Buffer Enable
OSC_OUT
0
1
OSCout Pin
Disabled (High Impedance)
Buffered output of OSCin pin
2.5.6 OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is
equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency presented to the RF R counter
is doubled. Phase noise added by the doubler is negligible.
OSC2X
0
Frequency Presented to RF R Counter
f
OSCin
2 x f
OSCin
Frequency Presented to IF R Counter
f
OSCin
1
2.5.7 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the carrier
by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least one
greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off.
FM
0
1
Function
Fractional PLL mode with a 4th order delta-sigma modulator
Disable the delta-sigma modulator. Recommended for test use
only.
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
2
3
2.5.8 DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also
give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also
increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the
loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional spurs
much, but has a much larger impact on the sub-fractional spurs. If it is decided that dithering will be used, best results will be
obtained when the fractional denominator is at least 1000.
DITH
0
1
2
3
Dithering Mode Used
Disabled
Weak Dithering
Strong Dithering
Reserved
2.5.9 ATPU -- PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0 register is written to,
the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when the CE pin is low. In this case,
the ATPU function is disabled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2487ESQ/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQE | 制造商:Texas Instruments 功能描述:PLL, 7.5GHZ, DUAL, DELTA SIGMA, SMD 制造商:Texas Instruments 功能描述:Delta-Sigma LPower Dual PLL,LMX2487ESQE |
| LMX2487ESQE/NOPB | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| LMX2487ESQNOPB | 制造商:National Semiconductor 功能描述:PLL Frequency Synthesizer Dual 5MHz to 7500MHz 24-Pin LLP EP T/R |
| LMX2487ESQX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:7.5 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 3.0 GHz Integer PLL |
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