參數(shù)資料
型號(hào): LMX2485SQX
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
中文描述: PLL FREQUENCY SYNTHESIZER, 3000 MHz, PQCC24
封裝: 4 X 4 MM, 0.8 MM, PLASTIC, LLP-24
文件頁數(shù): 27/37頁
文件大?。?/td> 861K
代理商: LMX2485SQX
Programming Description
(Continued)
2.2 R1 REGISTER
REGISTER
23
22
21
20
19
18
17
16
DATA[19:0]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3
0
C2
0
C1
1
C0
1
R1
RF_PD
RF_P
RF_R[5:0]
RF_FD[11:0]
2.2.1 RF_FD[11:0] -- RF PLL Fractional Denominator
The function of these bits are described in section 2.6.2.
2.2.2 RF_R [5:0] -- RF R Divider Value
The RF R Counter value is determined by this control word. Note that this counter does allow values down to one.
R Value
1
...
63
RF_R[5:0]
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
2.2.3 RF_P -- RF Prescaler bit
The prescaler used is determined by this bit.
RF_P
0
1
Prescaler
8/9/12/13
16/17/20/21
Maximum Frequency
2000 MHz
3000 MHz
2.2.4 RF_PD -- RF Power Down Control Bit
When this bit is set to 0, the RF PLL operates normally. When it is set to one, the RF PLL is powered down and the RF Charge
pump is set to a TRI-STATE mode. The CE pin and ATPU bit also control power down functions, and will override the RF_PD bit.
The order of precedence is as follows. First, if the CE pin is LOW, then the PLL will be powered down. Provided this is not the
case, the PLL will be powered up if the ATPU bit says to do so, regardless of the state of the RF_PD bit. After the CE pin and the
ATPU bit are considered, then the RF_PD bit then takes control of the power down function for the RF PLL.
L
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