參數(shù)資料
型號: LMX2485SQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: XO, clock
英文描述: 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
中文描述: PLL FREQUENCY SYNTHESIZER, 3000 MHz, PQCC24
封裝: 4 X 4 MM, 0.8 MM, PLASTIC, LLP-24
文件頁數(shù): 28/37頁
文件大?。?/td> 861K
代理商: LMX2485SQ
Programming Description
(Continued)
2.3 R2 REGISTER
REGISTER
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
DATA[19:0]
IF_N[18:0]
C3
0
C2
1
C1
0
C0
1
R2
IF_PD
2.3.1 IF_N[18:0] -- IF N Divider Value
IF_N Counter Programming with the 8/9 Prescaler (IF_P=0)
N Value
IF_N[18:0]
IF_B
IF_A
23
24-55
N values less than or equal to 23 are prohibited because IF_B
3 is required.
Legal divide ratios in this range are:
24-27, 32-36, 40-45, 48-54
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
.
.
.
.
.
.
1
1
1
1
1
1
1
56
57
...
0
0
.
1
0
0
.
1
0
0
.
1
0
0
.
1
0
0
.
1
1
1
.
1
1
1
.
1
1
1
.
1
0
0
.
0
0
0
.
1
0
0
.
1
0
1
.
1
262143
Operation with the 16/17 Prescaler (IF_P=1)
N Value
IF_B
IF_A
47
48-239
N values less than or equal to 47 are prohibited because IF_B
3 is required.
Legal divide ratios in this range are:
48-51, 64-68, 80-85, 96-102, 112-119, 128-136, 144-153, 160-170, 176-187, 192-204, 208-221, 224-238
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
.
.
.
.
.
.
.
.
.
1
1
1
1
1
1
1
1
1
240
241
...
524287
0
0
.
1
0
0
.
1
1
1
.
1
1
1
.
1
1
1
.
1
1
1
.
1
0
0
.
1
0
0
.
1
0
0
.
1
0
1
.
1
2.3.4 IF_PD -- IF Power Down Bit
When this bit is set to 0, the IF PLL operates normally. When it is set to 1, the IF PLL powers down and the output of the IF PLL
charge pump is set to a TRI-STATE mode. If the ATPU bit is set and register R0 is written to, the IF_PD will be reset to 0 and the
IF PLL will be powered up. If the CE pin is held low, the IF PLL will be powered down, overriding the IF_PD bit.
L
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