參數(shù)資料
型號: LMX2485_0610
廠商: National Semiconductor Corporation
英文描述: 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL
中文描述: 50兆赫- 3.0 GHz的高性能Δ-Σ低功耗雙PLLatinum⑩頻率合成器與800兆赫整數(shù)鎖相環(huán)
文件頁數(shù): 33/37頁
文件大?。?/td> 881K
代理商: LMX2485_0610
Programming Description
(Continued)
2.6 R5 REGISTER
REGISTER
23
22
21
20
19
18
17
16
15
DATA[19:0]
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
C3
1
C2
0
C1
1
C0
1
R5
RF_FD[21:12]
RF_FN[21:12]
2.6.1 Fractional Numerator Determination { RF_FN[21:12], RF_FN[11:0], ACCESS[1] }
In the case that the ACCESS[1] bit is 0, then the part operates in 12-bit fractional mode, and the RF_FN2[21:12] bits become do
not care bits. When the ACCESS[1] bit is set to 1, the part operates in 22-bit mode and the fractional numerator is expanded from
12 to 22-bits.
Fractional
Numerator
0
1
...
4095
4096
...
4194303
RF_FN[21:12]
RF_FN[11:0]
( These bits only apply in 22- bit mode)
In 12- bit mode, these are do not care.
In 22- bit mode, for N
<
4096,
these bits should be all set to 0.
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
1
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
2.6.2 Fractional Denominator Determination { RF_FD[21:12], RF_FD[11:0], ACCESS[1]}
In the case that theACCESS[1] bit is 0, then the part is operates in the 12-bit fractional mode, and the RF_FD[21:12] bits become
do not care bits. When the ACCESS[1] is set to 1, the part operates in 22-bit mode and the fractional denominator is expanded
from 12 to 22-bits.
Fractional
Denominator
0
1
...
4095
4096
...
4194303
RF_FD[21:12]
RF_FD[11:0]
( These bits only apply in 22- bit mode)
In 12- bit mode, these are do not care.
In 22- bit mode, for N
<
4096,
these bits should be all set to 0.
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
0
.
1
0
.
1
0
1
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
0
.
1
1
.
1
L
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