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參數(shù)資料
| 型號(hào)： | LMX2372MDC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 10/27頁 |
| 文件大小： | 550K |
| 代理商： | LMX2372MDC |
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2.0 Programming Description (Continued)
2.4.4 The FoLD Output Truth Table
Main
R[18]
Aux
R[18]
Main
R[19]
Aux
R[19]
Fo/LD Output State
0
Disabled
0
1
0
Aux Lock Detect (Note 10)
1
0
Main Lock Detect (Note 10)
1
0
Main/Aux Lock Detect (Note 10)
X
0
1
Aux Reference Divider Output
X
0
1
0
Main Reference Divider Output
X
1
0
1
Aux Programmable Divider Output
X
1
0
Main Programmable Divider Output
0
1
FastLock Output. Open Drain Output (Note 11)
0
1
Reset Aux R and N Counters and TRI-STATE Aux Charge Pump (Note 12)
1
0
1
Reset Main R and N Counters and TRI-STATE Main Charge Pump (Note
12)
1
Reset All Four Counters and TRI-STATE both Charge Pumps (Note 12)
X - don’t care condition
Note 10: Open drain lock detect output is provided to indicate when the VCO frequency is in “l(fā)ock”. When the loop is locked and a lock detect mode is selected,
the pin is HIGH, with narrow pulses LOW. In the Main/Aux lock detect mode a locked condition is indicated when Main and Aux are both locked.
Note 11: The FastLock mode utilizes the FoLD output pin to switch a second loop filter damping resistor to ground during FastLock operation. Activation of FastLock
occurs whenever the Main loop’s ICPo magnitude bit R[16] is selected HI while the R[18] and R[19] mode bits are set.
Note 12: Aux and Main PLLs can be reset independently from each other by using the R[18] and R[19] bits. The Aux Counter Reset mode resets Aux PLL’s R and
N counters and brings Aux charge pump output to TRI-STATE condition. The Main Counter Reset mode resets Main PLL’s R and N counters and brings Main charge
pump output to a TRI-STATE condition. The Aux and Main Counter Reset modes reset all counters and bring both charge pump outputs to a TRI-STATE condition.
Upon removal of the Reset bits, the N counter resumes counting in “close” alignment with the R counter. (The maximum error is one prescaler cycle.)
2.5 Serial Data Input Timing
Serial Data Input Timing
DS101026-6
NOTES: Parenthesis data indicates programmable reference divider data.
Data shifted into register on clock rising edge.
Data is shifted in MSB first.
TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around VCC/2. The test waveform has an edge rate of 0.6 V/ns with
amplitudes of 2.2V @ VCC = 2.7V and 2.6V @ VCC = 5.5V.
LMX2370/LMX2371/LMX2372
www.national.com
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