參數(shù)資料
型號(hào)： LMX2370TMX/NOPB
廠(chǎng)商： NATIONAL SEMICONDUCTOR CORP
元件分類(lèi)： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20
封裝： PLASTIC, TSSOP-20
文件頁(yè)數(shù)： 14/25頁(yè)
文件大小： 577K
代理商： LMX2370TMX/NOPB
Application Information
A block diagram of the basic phase locked loop is shown in
LOOP GAIN EQUATIONS
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (K
φ), the
VCO gain (K
VCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, while
the complex impedance of the filter is given in Equation (2).
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(3)
and
T2=R2
C2
(4)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency,
ω, the filter time constants T1 and T2,
and the design constants Kφ,KVCO, and N.
(5)
From Equation (3) we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in Equation (6).
φ(ω) = tan1 (ω T2) tan1 (ω T1) + 180
(6)
A plot of the magnitude and phase of G(s)H(s) for a stable
loop, is shown in Figure 4 with a solid trace. The parameter
φ
p shows the amount of phase margin that exists at the point
the gain drops below zero (the cutoff frequency wp of the
loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
If we were now to redefine the cut off frequency, wp’, as
double the frequency which gave us our original loop band-
width, wp, the loop response time would be approximately
halved. Because the filter attenuation at the comparison
frequency also diminishes, the spurs would have increased
by approximately 6 dB. In the proposed Fastlock scheme,
the higher spur levels and wider loop filter conditions would
exist only during the initial lock-on phase — just long enough
to reap the benefits of locking faster. The objective would be
to open up the loop bandwidth but not introduce any addi-
tional complications or compromises related to our original
design criteria. We would ideally like to momentarily shift the
curve of Figure 4 over to a different cutoff frequency, illus-
trated by the dotted line, without affecting the relative open
loop gain and phase relationships. To maintain the same
gain/phase relationship at twice the original cutoff frequency,
10102638
FIGURE 1. Basic Charge Pump Phase Locked Loop
10102639
FIGURE 2. PLL Linear Model
10102640
FIGURE 3. Passive Loop Filter
LMX2370
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LMX2371 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:
LMX2371 WAF 制造商:Texas Instruments 功能描述:
LMX2371SLBX 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2371TM 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2371TMX 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類(lèi)型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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