- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385492 > LMX2364TM (NATIONAL SEMICONDUCTOR CORP) 2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer PDF資料下載
參數(shù)資料
| 型號： | LMX2364TM |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | 2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2600 MHz, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 3/39頁 |
| 文件大?。?/td> | 694K |
| 代理商： | LMX2364TM |
第1頁第2頁當(dāng)前第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁
Pin Descriptions
Pin Number
TSSOP
2
Pin
Description
SLE
1
VccRF
RF PLL power supply voltage input. Must be equal to V
VccIF
. May range from 2.7V to
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
Power supply for RF charge pump. Must be
≥
V
VccRF
and V
VccIF
.
RF charge pump output.
Ground for RF PLL digital circuitry.
RF prescaler input. Small signal input from the VCO.
RF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground plane.
Ground for RF PLL analog circuitry.
RF R counter input. Has a V
CC
/2 input threshold when configured as an input and can
be driven from an external CMOS or TTL logic gate.
Oscillator input which can be configured to drive both the IF and RF R counter inputs
or only the IF R counter depending on the state of the OSC programming bit.
Programmable multiplexed output pin. Can function as general purpose CMOS
TRI-STATE
I/O, analog lock detect output, digital filtered lock detect output, or N & R
divider output.
RF PLL Enable. Powers down RF N and R counters, prescaler, and TRI-STATE
charge pump output when LOW, regardless of the state RF_PD bit. Bringing ENRF
high powers up RF PLL depending on the state of RF_PD control bit.
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the
charge pump output when LOW, regardless of the state IF_PD bit. Bringing ENIF high
powers up IF PLL depending on the state of IF_PD control bit.
High impedance CMOS Clock input. Data for the control registers is clocked into the
24-bit shift register on the rising edge.
Binary serial data input. Data entered MSB first. The last three bits are the control
bits. High impedance CMOS input.
Latch enable. High impedance CMOS input. Data stored in the shift register is loaded
into one of the 7 internal latches when LE goes HIGH.
Ground for IF analog circuitry.
IF prescaler complementary input. For single-ended operation, a bypass capacitor
should be placed as close as possible to this pin and be connected directly to the
ground.
IF prescaler input. Small signal input from the VCO.
Ground for IF digital circuitry.
IF charge pump output.
Power supply for IF charge pump. Must be
≥
V
VccRF
and V
VccIF
.
IF power supply voltage input. Must be equal to V
VccRF
. Input may range from 2.7V to
5.5V. Bypass capacitors should be placed as close as possible to this pin and be
connected directly to the ground plane.
IF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
RF FastLock Output. Also functions as Programmable TRI-STATE CMOS output.
3
4
5
6
7
2
3
4
5
6
VcpRF
CPoutRF
GND
FinRF
FinRF*
8
9
7
8
GND
OSCinRF
10
9
OSCinIF
11
10
Ftest/LD
12
11
ENRF
13
12
ENIF
14
13
CLK
15
14
DATA
16
15
LE
17
18
16
17
GND
FinIF*
19
20
21
22
23
18
19
20
21
22
FinIF
GND
CPoutIF
VcpIF
VccIF
24
1
23
24
FLoutIF
FLoutRF
L
www.national.com
3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2364TMX | 2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
| LMX2370 | PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個人通訊的雙通道頻率合成器) |
| LMX2371 | PLLatinum Dual Frequency Synthesizer for RF Personal Communications(PLLatinum技術(shù)用于射頻個人通訊的雙通道頻率合成器) |
| LMX2411 | Baseband Processor for Radio Communications |
| LMX2485_0610 | 50 MHz - 3.0 GHz High Performance Delta-Sigma Low Power Dual PLLatinum⑩ Frequency Synthesizers with 800 MHz Integer PLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2364TM/NOPB | 功能描述:IC FREQ SYNTH 2.6GHZ 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2364TMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer |
| LMX2364TMX/NOPB | 功能描述:IC FREQ SYNTH 2.6GHZ 24-TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2370 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| LMX2370SLBX | 功能描述:IC FREQ SYNTH DUAL 24LAMINATECSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計(jì)時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。