參數(shù)資料
型號(hào)： LMX2364
廠商： National Semiconductor Corporation
英文描述： 2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer
中文描述： 2.6千兆赫PLLatinum分?jǐn)?shù)RF頻率合成器850 MHz的IF頻率合成器整數(shù)
文件頁(yè)數(shù)： 23/39頁(yè)
文件大小： 694K
代理商： LMX2364
Functional Description
1.0 GENERAL
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX2364, a volt-
age controlled oscillator (VCO), and a passive loop filter. The
frequency synthesizer includes a phase detector, charge
pump, and programmable frequency dividers. These divid-
ers are the reference [R] and feedback [N] frequency divid-
ers. The VCO frequency is established by dividing the crystal
reference signal down via the R counter to obtain a fre-
quency in order to establish the comparison frequency. This
comparison frequency, f
COMP
, is input to the phase detector,
which compares this signal to another signal, f
, the feed-
back signal. f
is the result of dividing the VCO frequency
down by way of the N counter and fractional circuitry. The
phase/frequency detector’s charge pump outputs a current
into the loop filter, which is then converted into the VCO’s
control voltage. The phase/frequency comparator’s function
is to adjust the voltage presented to the VCO until the
feedback signal’s frequency (and phase) match that of the
reference signal. When this ‘phase-locked’ condition exists,
the VCO’s frequency will be N+F times that of the compari-
son frequency, where N is the integer component of the
divide ratio and F is the fractional component. Fractional
synthesis allows the phase detector frequency to be in-
creased while maintaining the same frequency step size for
channel selection. The division value N is thereby reduced
giving a lower phase noise referred to the phase detector
input, and the comparison frequency is increased allowing
faster switching times.
1.1 OPERATING MODES
The LMX2364 RF PLL is a capable of operating as both a
Fractional N synthesizer and an Integer N synthesizer. Op-
erating in Fractional mode is likely to yield the best phase
noise, but Integer mode often yields the lowest spur levels.
The operating mode is determined by the RF_OM[1:0] word.
It is possible to cause this PLL to behave as an integer PLL
in fractional mode by setting the fractional numerator,
RF_FN, to zero and disabling the fractional compensation
that is controlled by the FE bit. However, by actually setting
the part to Integer mode allows the range of the counters to
be extended.
1.2 POWER DOWN
The LMX2364 can be powered down via the two software
bits and the two enable pins. The RF PLL is only powered up
when the ENRF pin is high and the RF_PD bit ( R4[23] ) is
low. In a similar manner, the IF PLL is powered up only when
the ENIF pin is high and the IF_PD bit ( R1[23] ) is low.
1.3 OSCILLATOR
The OSCinRF and OSCinIFpins are used to drive the R
dividers for the RF and IF PLLs. In the case that the OSC Bit
( R6[7] ) is set to 0, the RF R counter is driven by the
OSCinRF pin and the IF R counter is driven independently of
this by the OSCinIF pin. In the case that both R counters are
to be driven with the same frequency, this bit needs to be set
to one. This PLL does not support the use of a crystal in any
mode.
L
www.national.com
23
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LMX2364SLEX 制造商:NSC 制造商全稱:National Semiconductor 功能描述:2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer
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LMX2364TM 制造商:NSC 制造商全稱:National Semiconductor 功能描述:2.6 GHz PLLatinum Fractional RF Frequency Synthesizer with 850 MHz Integer IF Frequency Synthesizer
LMX2364TM/NOPB 功能描述:IC FREQ SYNTH 2.6GHZ 24TSSOP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無(wú)/無(wú) 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
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