參數(shù)資料
型號(hào)： LMX2352SLBX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 1200 MHz, PQCC24
封裝： LAMINATE, CSP-24
文件頁(yè)數(shù)： 12/26頁(yè)
文件大小： 465K
代理商： LMX2352SLBX
Connection Diagram
Pin Descriptions
Pin
No.
Pin
Name
I/O
Description
1
OUT0
O
Programmable CMOS output. Level of the output is controlled by IF_N [17] bit.
2
Vcc
RF
-
RF PLL power supply voltage input. Must be equal to Vcc
IF. May range from 2.7 V to 5.5 V.
Bypass capacitors should be placed as close as possible to this pin and be connected directly
to the ground plane.
3V
pRF
-
Power supply for RF charge pump. Must be
≥V
ccRF and VccIF.
4CP
oRF
O
RF charge pump output. Connected to a loop filter for driving the control input of an external
VCO.
5
GND
-
Ground for RF PLL digital circuitry.
6
fin RF
I
RF prescaler input. Small signal input from the VCO.
7
fin RF
I
RF prescaler complimentary input. A bypass capacitor should be placed as close as possible
to this pin and be connected directly to the ground plane.
8
GND
-
Ground for RF PLL analog circuitry.
9
OSCx
I/O
Dual mode oscillator output or RF R counter input. Has a Vcc/2 input threshold when
configured as an input and can be driven from an external CMOS or TTL logic gate. Can also
be configured as an output to work in conjunction with OSCin to form a crystal oscillator. (See
functional description 1.1 and programming description 3.1.)
10
OSCin
I
Oscillator input which can be configured to drive both the IF and RF R counter inputs or only
the IF R counter depending on the state of the OSC programming bit. (See functional
description 1.1 and programming description 3.1.)
11
FoLD
O
Multiplexed output of N or R divider and RF/IF lock detect. Active High/Low CMOS output
except in analog lock detect mode. (See programming description 3.1.5.)
12
RF_EN
I
RF PLL Enable. Powers down RF N and R counters, prescaler, and will TRI-STATE the
charge pump output when LOW. Bringing RF_EN high powers up RF PLL depending on the
state of RF_CTL_WORD. (See functional description 1.9.)
13
IF_EN
I
IF PLL Enable. Powers down IF N and R counters, prescaler, and will TRI-STATE the charge
pump output when LOW. Bringing IF_EN high powers up IF PLL depending on the state of
IF_CTL_WORD. (See functional description 1.9.)
14
CLOCK
I
High impedance CMOS Clock input. Data for the various counters is clocked into the 24 - bit
shift register on the rising edge.
15
DATA
I
Binary serial data input. Data entered MSB first. The last two bits are the control bits. High
impedance CMOS input.
16
LE
I
Load enable high impedance CMOS input. Data stored in the shift registers is loaded into one
of the 4 internal latches when LE goes HIGH. (See functional description 1.7.)
DS100831-2
Order Number LMX2350TM or LMX2352TM
NS Package Number MTC24
www.national.com
2
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PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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