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參數(shù)資料
| 型號(hào)： | LMX2335LTMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 10/24頁 |
| 文件大?。?/td> | 631K |
| 代理商： | LMX2335LTMX/NOPB |
Application Information
A block diagram of the basic phase locked loop is shown in
Loop Gain Equations
A linear control system model of the phase feedback for a
PLL in the locked state is shown in Figure 2. The open loop
gain is the product of the phase comparator gain (Kφ), the
VCO gain (K
VCO/s), and the loop filter gain Z(s) divided by
the gain of the feedback counter modulus (N). The passive
loop filter configuration used is displayed in Figure 3, WHILE
the complex impedance of the filter is given in equation 2.
(1)
(2)
The time constants which determine the pole and zero fre-
quencies of the filter transfer function can be defined as
(3)
The 3rd order PLL Open Loop Gain can be calculated in
terms of frequency,
ω, the filter time contants T1 and T2, and
the design constants K
φ,K
VCO, and N.
(4)
From Equation (3) we can see that the phase term will be
dependent on the single pole and zero such that the phase
margin is determined in Equation (1).
φ(ω) = tan1 (ω T2) tan1 (ω T1) + 180C
(5)
A plot of the magnitude and phase of G(s) H(s) for a stable
loop, is shown in Equation (4) with a solid trace. The param-
eter
φ
p shows the amount of phase margin that exists at the
point the gain drops below zero (the cutoff frequency wp of
the loop). In a critically damped system, the amount of phase
margin would be approximately 45 degrees.
01280713
FIGURE 1. Conventional PLL Architecture
01280714
FIGURE 2. PLL Linear Model
01280715
FIGURE 3. Passive Loop Filter
LMX2335L/LMX2336L
www.national.com
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