參數(shù)資料
型號： LMX2332USLBX
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： XO, clock
英文描述： PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
中文描述： PLL FREQUENCY SYNTHESIZER, 1200 MHz, PQCC24
封裝： PLASTIC, CSP-24
文件頁數(shù)： 30/42頁
文件大?。?/td> 3318K
代理商： LMX2332USLBX
1.0 Functional Description
The basic phase-lock-loop (PLL) configuration consists of a
high-stability crystal reference oscillator, a frequency synthe-
sizer such as the National Semiconductor LMX233xU, a
voltage controlled oscillator (VCO), and a passive loop filter.
The frequency synthesizer includes a phase detector, cur-
rent mode charge pump, programmable reference R and
feedback N frequency dividers. The VCO frequency is es-
tablished by dividing the crystal reference signal down via
the reference divider to obtain a comparison reference fre-
quency. This reference signal, F
, is then presented to the
input of a phase/frequency detector and compared with the
feedback signal, F
, which was obtained by dividing the VCO
frequency down by way of the feedback divider. The
phase/frequency detector measures the phase error be-
tween the F
r
and F
p
signals and outputs control signals that
are directly proportional to the phase error. The charge pump
then pumps charge into or out of the loop filter based on the
magnitude and direction of the phase error. The loop filter
converts the charge into a stable control voltage for the
VCO. The phase/frequency detector’s function is to adjust
the voltage presented to the VCO until the feedback signal’s
frequency and phase match that of the reference signal.
When this “Phase-Locked” condition exists, the VCO fre-
quency will be N times that of the comparison frequency,
where N is the feedback divider ratio.
1.1 REFERENCE OSCILLATOR INPUT
The reference oscillator frequency for both the RF and IF
PLLs is provided from an external reference via the OSC
in
pin. The reference buffer circuit supports input frequencies
from 5 to 40 MHz with a minimum input sensitivity of 0.5 V
.
The reference buffer circuit has an approximate V
/2 input
threshold and can be driven from an external CMOS or TTL
logic gate. Typically, the OSC
in
pin is connected to the output
of a crystal oscillator.
1.2 REFERENCE DIVIDERS (R COUNTERS)
The reference dividers divide the reference input signal,
OSC
, by a factor of R. The output of the reference divider
circuits feeds the reference input of the phase detector. This
reference input to the phase detector is often referred to as
the comparison frequency. The divide ratio should be chosen
such that the maximum phase comparison frequency (F
φ
RF
or F
φ
IF
) of 10 MHz is not exceeded.
The RF and IF reference dividers are each comprised of
15-bit CMOS binary counters that support a continuous in-
teger divide ratio from 3 to 32767. The RF and IF reference
divider circuits are clocked by the output of the reference
buffer circuit which is common to both.
1.3 PRESCALERS
The f
RF (f
IF) and f
RF (f
IF) input pins drive the input
of a bipolar, differential-pair amplifier. The output of the bi-
polar, differential-pair amplifier drives a chain of ECL D-type
flip-flops in a dual modulus configuration. The output of the
prescaler is used to clock the subsequent feedback dividers.
The RF and IF PLL complementary inputs can be driven
differentially, or the negative input can be AC coupled to
ground through an external capacitor for single ended con-
figuration. A 32/33 or a 64/65 prescale ratio can be selected
for the 2.5 GHz LMX2330U RF synthesizer. A 64/65 or a
128/129 prescale ratio can be selected for both the
LMX2331U and LMX2332U RF synthesizers. The IF circuitry
contains an 8/9 or a 16/17 prescaler.
1.4 PROGRAMMABLE FEEDBACK DIVIDERS (N
COUNTERS)
The programmable feedback dividers operate in concert with
the prescalers to divide the input signal, f
, by a factor of N.
The output of the programmable reference divider is pro-
vided to the feedback input of the phase detector circuit. The
divide ratio should be chosen such that the maximum phase
comparison frequency (F
φ
RF
or F
φ
IF
) of 10 MHz is not ex-
ceeded.
The programmable feedback divider circuit is comprised of
an A counter (swallow counter) and a B counter (program-
mble binary counter). The RF N_CNTRA counter is a 7-bit
CMOS swallow counter, programmable from 0 to 127. The IF
N_CNTRA counter is also a 7-bit CMOS swallow counter,
but programmable from 0 to 15. The three most significant
bits are ’don’t cares’ in this case. The RF N_CNTRB and IF
N_CNTRB counters are both 11-bit CMOS binary counters,
programmable from 3 to 2047. A continuous integer divide
ratio is achieved if N
≥
P
*
(P1), where P is the value of the
prescaler selected. Divide ratios less than the minimum con-
tinuous divide ratio are achievable as long as the binary
programmable counter value is greater than the swallow
counter value (N_CNTRB
≥
N_CNTRA). Refer to
Sections
2.6.1, 2.6.2, 2.7.1
and
2.7.2
for details on how to program
the N_CNTRA and N_CNTRB counters. The following equa-
tions are useful in determining and programming a particular
value of N:
N = (P x N_CNTRB) + N_CNTRA
f
IN
= N x F
φ
Definitions:
F
φ
:
RF
or
IF
phase
frequency
f
IN
:
RF or IF input frequency
N_CNTRA: RF or IF A counter value
N_CNTRB: RF or IF B counter value
P:
Preset
modulus
prescaler
LMX2330U RF synthesizer: P = 32 or 64
LMX2331U RF synthesizer: P = 64 or 128
LMX2332U RF synthesizer: P = 64 or 128
LMX233xU IF synthesizer: P = 8 or 16
detector
comparison
of
the
dual
moduIus
1.5 PHASE/FREQUENCY DETECTORS
The RF and IF phase/frequency detectors are driven from
their respective N and R counter outputs. The maximum
frequency for both the RF and IF phase detector inputs is 10
MHz. The phase/frequency detector outputs control the re-
spective charge pumps. The polarity of the pump-up or
pump-down control signals are programmed using the
PD-
_POL RF
or
PD_POL IF
control bits, depending on whether
the RF or IF VCO characteristics are positive or negative.
Refer to
Sections 2.4.2
and
2.5.2
for more details. The
phase/frequency detectors have a detection range of 2
π
to
+2
π
. The phase/frequency detectors also receive a feedback
signal from the charge pump in order to eliminate dead zone.
L
www.national.com
30
相關(guān)PDF資料
PDF描述
LMX2332UTM PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
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LMX2335M PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
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參數(shù)描述
LMX2332USLEX 功能描述:IC FREQ SYNTH DUAL 20LAMUCSP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2332UTM 功能描述:IC FREQ SYNTHESIZER DUAL 20TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:*
LMX2332UTMX 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications
LMX2334ATMX 制造商:Rochester Electronics LLC 功能描述:- Bulk
LMX2335 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications
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