- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄44574 > LMX2331USLEX (NATIONAL SEMICONDUCTOR CORP) PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC24 PDF資料下載
參數(shù)資料
| 型號： | LMX2331USLEX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC24 |
| 封裝： | PLASTIC, UTCSP-24 |
| 文件頁數(shù)： | 33/49頁 |
| 文件大?。?/td> | 4568K |
| 代理商： | LMX2331USLEX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當(dāng)前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁
1.0 Functional Description (Continued)
1.8.2 Open Drain FastLock Output
The LMX233xU Fastlock feature allows faster loop response
time during lock aquisition. The loop response time (lock
time) can be approximately halved if the loop bandwidth is
doubled. In order to achieve this, the same gain/ phase
relationship at twice the loop bandwidth must be maintained.
This can be achieved by increasing the charge pump current
from 0.95 mA (ID
o RF Bit = 0) in the steady state mode, to
3.8 mA (ID
o RF Bit = 1) in Fastlock. When the FoLD output is
configured as a FastLock output, an open drain device is
enabled. The open drain device switches in a parallel resis-
tor R2’ to ground, of equal value to resistor R2 of the external
loop filter. The loop bandwidth is effectively doubled and
stability is maintained. Once locked to the correct frequency,
the PLL will return to a steady state condition. Refer to
Section 2.8 F
oLD for details on how to configure the FoLD
output to an open drain Fastlock output.
1.8.3 Counter Reset
Three separate counter reset functions are provided. When
the F
oLD is programmed to Reset IF Counters, both the IF
feedback divider and the IF reference divider are held at their
load point. When the Reset RF Counters is programmed,
both the RF feedback divider and the RF reference divider
are held at their load point. When the Reset All Counters
mode is enabled, all feedback dividers and reference divid-
ers are held at their load point. When the device is pro-
grammed to normal operation, both the feedback divider and
reference divider are enabled and resume counting in ‘close’
alignment to each other. Refer to Section 2.8 F
oLD for more
details.
1.8.4 Reference Divider and Feedback Divider Output
The outputs of the various N and R dividers can be moni-
tored by selecting the appropriate F
oLD word. This is essen-
tial when performing OSC
in or fIN sensitivity measurements.
Refer to the Test Setups section for more details. Refer to
Section 2.8 F
oLD for more details on how to route the
appropriate divider output to the F
oLD pin.
1.9 POWER CONTROL
Each synthesizer in the LMX233xU device is individually
power controlled by device powerdown bits. The powerdown
word is comprised of the PWDN RF (PWDN IF) bit, in
conjuction with the TRI-STATE ID
o RF (TRI-STATE IDo IF)
bit. The powerdown control word is used to set the operating
mode of the device. Refer to Sections 2.4.4, 2.5.4, 2.6.4,
and 2.7.4 for details on how to program the RF or IF power-
down bits.
When either the RF synthesizer or the IF synthesizer enters
the powerdown mode, the respective prescaler, phase de-
tector, and charge pump circuit are disabled. The D
o RF (Do
IF), f
IN RF (fIN IF), and fIN RF (fIN IF) pins are all forced to a
high impedance state. The reference divider and feedback
divider circuits are held at the load point during powerdown.
The oscillator buffer is disabled when both the RF and IF
synthesizers are powered down. The OSC
in pin is forced to
a HIGH state through an approximate 100 k
resistance
when this condition exists. When either synthesizer is acti-
vated, the respective prescaler, phase detector, charge
pump circuit, and the oscillator buffer are all powered up.
The feedback divider, and the reference divider are held at
load point. This allows the reference oscillator, feedback
divider, reference divider and prescaler circuitry to reach
proper bias levels. After a finite delay, the feedback and
reference dividers are enabled and they resume counting in
‘close’ alignment (the maximum error is one prescaler cycle).
The MICROWIRE control register remains active and ca-
pable of loading and latching data while in the powerdown
mode.
Synchronous Powerdown Mode
In this mode, the powerdown function is gated by the charge
pump. When the device is configured for synchronous pow-
erdown, the device will enter the powerdown mode upon
completion of the next charge pump pulse event.
Asynchronous Powerdown Mode
In this mode, the powerdown function is NOT gated by the
completion of a charge pump pulse event. When the device
is configured for asynchronous powerdown, the part will go
into powerdown mode immediately.
TRI-STATE ID
o
PWDN
Operating Mode
0
PLL Active, Normal Operation
1
0
PLL Active, Charge Pump Output in High Impedance State
0
1
Synchronous Powerdown
1
Asynchronous Powerdown
Notes:
1. TRI-STATE ID
o refers to either the TRI-STATE IDo RF or TRI-STATE IDo IF bit .
2. PWDN refers to either the PWDN RF or PWDN IF bit.
LMX2330U/LMX2331U/LMX2332U
www.national.com
39
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2330UTMX/NOPB | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| LMX2335LTMX/NOPB | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| LMX2335LMX | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| LMX2335LTM/NOPB | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16 |
| LMX2336LTMX/NOPB | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2331USLEX/NOPB | 功能描述:IC FREQ SYNTH DUAL 20LAMUCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2331UTM | 功能描述:IC FREQ SYNTHESIZER DUAL 20TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| LMX2331UTMX | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2332 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2332A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。