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參數(shù)資料
| 型號(hào)： | LMX2331USLBX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PQCC24 |
| 封裝： | PLASTIC, CSP-24 |
| 文件頁數(shù)： | 31/42頁 |
| 文件大?。?/td> | 3318K |
| 代理商： | LMX2331USLBX |
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1.0 Functional Description
(Continued)
PHASE COMPARATOR AND INTERNAL CHARGE
PUMP CHARACTERISTICS
10136611
Notes:
1.
2.
3.
4.
5.
The minimum width of the pump-up and pump-down current pulses occur at the D
o
RF or D
o
IF pins when the loop is phase locked.
The diagram assumes positive VCO characteristics, i.e. PD_POL RF or PD_POL IF = 1.
F
r
is the phase detector input from the reference divider (R counter).
F
p
is the phase detector input from the programmable feedback divder (N counter).
D
o
refers to either the RF or IF charge pump output.
1.6 CHARGE PUMPS
The charge pump directs charge into or out of an external
loop filter. The loop filter converts the charge into a stable
control voltage which is applied to the tuning input of the
VCO. The charge pump steers the VCO control voltage
towards V
RF or V
IF during pump-up events and towards
GND during pump-down events. When locked, D
RF or D
o
IF are primarily in a TRI-STATE mode with small corrections
occuring at the phase comparator rate. The charge pump
output current magnitude can be selected by toggling the
ID
o
RF
or
ID
o
IF
control bits.
1.7 MICROWIRE SERIAL INTERFACE
The programmable register set is accessed via the MI-
CROWIRE serial interface. The interface is comprised of
three signal pins: Clock, Data and LE (Latch Enable). Serial
data is clocked into the 22-bit shift register on the rising edge
of Clock. The last two bits decode the internal control regis-
ter address. When LE transitions HIGH, data stored in the
shift register is loaded into one of four control registers
depending on the state of the address bits. The MSB of Data
is loaded in first. The synthesizers can be programmed even
in power down mode. A complete programming description
is provided in
Section 2.0 Programming Description
.
1.8 MULTI-FUNCTION OUTPUTS
The LMX233xU device’s F
o
LD output pin is a multi-function
output that can be configured as the RF FastLock output, a
push-pull analog lock detect output, counter reset, or used to
monitor the output of the various reference divider (R
counter) or feedback divider (N counter) circuits. The F
LD
control word is used to select the desired output function.
When the PLL is in powerdown mode, the F
LD output is
pulled to a LOW state. A complete programming description
of the multi-function output is provided in
Section 2.8 F
o
LD
.
1.8.1 Push-Pull Analog Lock Detect Output
An analog lock detect status generated from the phase
detector is available on the F
LD output pin if selected. The
lock detect output goes HIGH when the charge pump is
inactive. It goes LOW when the charge pump is active during
a comparison cycle. When viewed with an oscilloscope,
narrow negative pulses are observed when the charge pump
turns on. The lock detect output signal is a push-pull con-
figuration.
Three separate lock detect signals are routed to the multi-
plexer. Two of these monitor the ‘lock’ status of the individual
synthesizers. The third detects the condition when both the
RF and IF synthesizers are in a ‘locked state’. External
circuitry however, is required to provide a steady DC signal
to indicate when the PLL is in a locked state. Refer to
Section 2.8 F
o
LD
for details on how to program the different
lock detect options.
L
www.national.com
31
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