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參數(shù)資料
| 型號(hào)： | LMX2330UTMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數(shù)： | 3/42頁 |
| 文件大?。?/td> | 3318K |
| 代理商： | LMX2330UTMX |
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Connection Diagrams
Chip Scale Package (SLB)
(Top View)
Thin Shrink Small Outline Package (TM)
(Top View)
10136639
10136602
Pin Descriptions
Pin
Name
V
CC
Pin No.
24-Pin CSP
24
Pin No.
20-Pin TSSOP
1
I/O
Description
—
Power supply bias for the RF PLL analog and digital circuits. V
CC
may
range from 2.7V to 5.5V. Bypass capacitors should be placed as close as
possible to this pin and be connected directly to the ground plane.
RF PLL charge pump power supply. Must be
≥
V
CC
.
RF PLL charge pump output. The output is connected to the external loop
filter, which drives the input of the VCO.
Ground for the RF PLL digital circuitry.
RF PLL prescaler input. Small signal input from the VCO.
RF PLL prescaler complementary input. For single ended operation, this
pin should be AC grounded. The LMX233xU RF PLL can be driven
differentially when the bypass capacitor is omitted.
Ground for the RF PLL analog circuitry.
Reference oscillator input. The input has an approximate V
CC
/2 threshold
and can be driven from an external CMOS or TTL logic gate.
Ground for the IF PLL digital circuits, MICROWIRE
, F
o
LD, and oscillator
circuits.
Programmable multiplexed output pin. Functions as a general purpose
CMOS TRI-STATE output, RF/IF PLL push-pull analog lock detect output,
N and R divider output or Fastlock output, which connects a parallel
resistor to the external loop filter.
MICROWIRE Clock input. High impedance CMOS input. Data is clocked
into the 22-bit shift register on the rising edge of Clock.
MICROWIRE Data input. High impedance CMOS input. Binary serial data.
The MSB of Data is shifted in first. The last two bits are the control bits.
MICROWIRE Latch Enable input. High impedance CMOS input. When LE
transitions HIGH, Data stored in the shift register is loaded into one of 4
internal control registers.
Ground for the IF PLL analog circuitry.
V
P
RF
D
o
RF
2
3
2
3
—
O
GND
f
IN
RF
f
IN
RF
4
5
6
4
5
6
—
I
I
GND
OSC
in
7
8
7
8
—
I
GND
10
9
—
F
o
LD
11
10
O
Clock
12
11
I
Data
14
12
I
LE
15
13
I
GND
16
14
—
L
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相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LMX2331USLBX | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2331UTM | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2331UTMX | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2332USLBX | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2332UTM | PLLatinum Ultra Low Power Dual Frequency Synthesizer for RF Personal Communications |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LMX2331 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Low Power Dual Frequency Synthesizer for RF Personal Communications |
| LMX2331 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2331A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinum⑩ Dual Frequency Synthesizer for RF Personal Communications |
| LMX2331ATM | 制造商:Texas Instruments 功能描述: |
| LMX2331ATMX | 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:PLLatinum™ 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
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