參數(shù)資料
型號(hào): LMX2330UTMX/NOPB
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類(lèi): PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 2500 MHz, PDSO20
封裝: 0.173 INCH, PLASTIC, TSSOP-20
文件頁(yè)數(shù): 29/49頁(yè)
文件大小: 4568K
代理商: LMX2330UTMX/NOPB
Test Setups (Continued)
LMX233xU f
IN Impedance Test Setup
10136679
The block diagram above illustrates the setup required to
measure the LMX233xU device’s RF input impedance. The
IF input impedance and reference oscillator impedance set-
ups are very much similar. The same setup is used for the
LMX2330TMEB/ LMX2330SLEEB Evaluation Boards. Mea-
suring the device’s input impedance facilitates the design of
appropriate matching networks to match the PLL to the VCO,
or in more critical situations, to the characteristic impedance
of the printed circuit board (PCB) trace, to prevent undesired
transmission line effects.
Before the actual measurements are taken, the Network
Analyzer needs to be calibrated, i.e. the error coefficients
need to be calculated. Therefore, three standards will be
used to calculate these coefficients: an open, short and a
matched load. A 1-port calibration is implemented here.
To calculate the coefficients, the PLL chip is first removed
from the PCB. The Network Analyzer port is then connected
to the RF OUT connector of the evaluation board and the
desired operating frequency is set. The typical frequency
range selected for the LMX233xU device’s RF synthesizer is
from 100 MHz to 2500 MHz. The standards will be located
down the length of the RF OUT transmission line. The trans-
mission line adds electrical length and acts as an offset from
the reference plane of the Network Analyzer; therefore, it
must be included in the calibration. Although not shown, 0
resistors are used to complete the RF OUT transmission line
(trace).
To implement an open standard, the end of the RF OUT
trace is simply left open. To implement a short standard, a 0
resistor is placed at the end of the RF OUT transmission
line. Last of all, to implement a matched load standard, two
100
resistors in parallel are placed at the end of the RF
OUT transmission line. The Network Analyzer calculates the
calibration coefficients based on the measured S
11 param-
eters. With this all done, calibration is now complete.
The PLL chip is then placed on the PCB. A power supply is
connected to V
CC and swept from 2.7V to 5.5V. The OSCin
pin is tied to the ground plane. Alternatively, the OSC
in pin
can be tied to V
CC. In this setup, the complementary input
(f
IN RF) is AC coupled to ground. With the Network Analyzer
still connected to RF OUT, the measured f
IN RF impedance
is displayed.
Note: The impedance of the reference oscillator is measured
when the oscillator buffer is powered up (PWDN RF Bit = 0
or PWDN IF Bit = 0), and when the oscillator buffer is
powered down (PWDN RF Bit = 1 and PWDN IF Bit = 1).
LMX2330U/LMX2331U/LMX2332U
www.national.com
35
相關(guān)PDF資料
PDF描述
LMX2335LTMX/NOPB PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16
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LMX2335LTM/NOPB PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO16
LMX2336LTMX/NOPB PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO20
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