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參數(shù)資料
| 型號(hào)： | LMX2326TMX/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2800 MHz, PDSO16 |
| 封裝： | 0.173 INCH, LEAD FREE, PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大?。?/td> | 342K |
| 代理商： | LMX2326TMX/NOPB |
2.0 Application Information
(Continued)
2.9 FastLock MODE 1 PROGRAMMING
The F[1]–F[7] bits will be denoted as (*) and are dependent
on the desired modes of the applicable functions. To pro-
gram the device for mode 1 FastLock, the F[8]–F[10] bits are
programmed 100, while the N[19] bit is set to 1. The device
will stay in the 4X current mode until another N bit stream is
sent with the N[19] bit reset to 0. This gives a bit stream as
follows:
10012717
2.10 FastLock MODE 2 PROGRAMMING
Again, the F[1]–F[7] bits will be denoted as don’t care (*) but
are dependent on the desired modes of the applicable func-
tions. To program the device for mode 2 FastLock, the
F[8]–F[10] bits are programmed 101, while the N[19] bit is
set to 1. The device will stay in the 4X current mode for the
programmed
number
of
phase
detector
cycles.
Bits
F[11]–F[14] program this number of cycles and are shown in
Table 6. For our example, we will use 27 phase detector
cycles, i.e. bits F[11]–F[14] will be 0110
b. After 27 phase
detector cycles, the N[19] bit returns to zero, bringing the
device back to low current mode. The resulting bit stream is
as follows:
10012718
FastLock modes 3 and 4 are programmed in the same
manner and give the added 4X gain increase as discussed in
Section 1.3.4 FastLock modes.
LMX2306/LMX2316/LMX2326
www.national.com
17
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