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參數(shù)資料
| 型號： | LMX2315WG-QMLX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 1200 MHz, CDSO20 |
| 封裝： | 0.300 INCH, CERAMIC, SOIC-20 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大?。?/td> | 132K |
| 代理商： | LMX2315WG-QMLX |
MNLMX2315-X REV 2B1
MICROCIRCUIT DATA SHEET
Electrical Characteristics
AC PARAMETERS:
SYMBOL
PARAMETER
CONDITIONS
NOTES
PIN-
NAME
MIN
MAX
UNIT
SUB-
GROUPS
tCS
Data to Clock
Setup Time
See Data Input Timing for Figure 3
4
50
nS
9, 10,
11
tCH
Data to Clock
Hold Time
See Data Input Timing for Figure 3
4
10
nS
9, 10,
11
tCWH
Clock Pulse Width
High
See Data Input Timing for Figure 3
4
50
nS
9, 10,
11
tCWL
Clock Pulse Width
Low
See Data Input Timing for Figure 3
4
50
nS
9, 10,
11
tES
Clock to Enable
Setup Time
See Data Input Timing for Figure 3
4
50
nS
9, 10,
11
tEW
Enable Pulse
Width
See Data Input Timing for Figure 3
4
50
nS
9, 10,
11
fIN
Maximum Operating
Frequency
Divide Ratio 193, fout (diff) = +322Hz
5
1.2
GHz
9, 10,
11
Divide Ratio 385, fout (diff) = +243Hz
5
1.2
GHz
9, 10,
11
Pfin
Input Sensitivity
Vcc = 2.7V
4
-15
+5
dBm
9, 10,
11
Vcc = 5.5V
4
-9
+6
dBm
9, 10
4
-7
+6
dBm
11
Locktime
Freq. Jump 51MHz (f = 864 to 915Mhz),
lock time within +5KHz, Vcc = Vp =
5.0V
3
500
uS
9
Phase Noise
fop = 900Mhz at 1KHz offset, Vcc = Vp
= 5.0V
3
-70
dBc
9
fop = 900Mhz at 10KHz offset, Vcc = Vp
= 5.0V
3
-70
dBc
9
Spurs
fop = 900Mhz, fref = 200KHz, Vcc = Vp
= 5.0V
3
-60
dBc
9
DC PARAMETERS: DRIFT VALUES
(The following conditions apply to all the following parameters, unless otherwise specified.)
DC:
Delta calculations performed on -MLS devices at group B, subgroup 5.
Icc_pwdn
Power Down
current
Vcc=2.7V
3
-20
20
uA
1
Vcc=5.5V
3
-40
40
uA
1
Ido_tri
Charge Pump
Tri-State current
0.5V<Vdo<3.1V, Vcc=Vp=3.6V
*or +100%
of initial value whichever is greater
3
-250
250*
pA
1
Note 1:
Except fIN and OSCin.
Note 2:
Except OSCout.
Note 3:
QMLV/MLS only
Note 4:
Used as Setup Conditions for Functional Testing.
6
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