
Connection Diagrams
LMX2314
TL/W/11766–2
JEDEC 16-Lead (0.150
×
Wide) Small
Outline Molded Package (M)
Order Number LMX2314M or LMX2314MX
See NS Package Number M16A
LMX2315
TL/W/11766–3
20-Lead (0.173
×
Wide) Thin Shrink
Small Outline Package (TM)
Order Number LMX2315TM or LMX2315TMX
See NS Package Number MTC20
Pin Descriptions
Pin No.
Pin No.
Pin Name
I/O
Description
2314
2315
2314/2315
1
1
OSC
IN
I
Oscillator input. A CMOS inverting gate input intended for connection to a crystal
resonator for operation as an oscillator. The input has a V
/2 input threshold and
can be driven from an external CMOS or TTL logic gate. May also be used as a
buffer for an externally provided reference oscillator.
2
3
OSC
OUT
V
P
V
CC
O
Oscillator output.
Power supply for charge pump. Must be
t
V
CC
.
Power supply voltage input. Input may range from 2.7V to 5.5V. Bypass capacitors
should be placed as close as possible to this pin and be connected directly to the
ground plane.
3
4
4
5
5
6
D
o
O
Internal charge pump output. For connection to a loop filter for driving the input of
an external VCO.
6
7
GND
Ground.
7
8
LD
O
Lock detect. Output provided to indicate when the VCO frequency is in ‘‘lock’’.
When the loop is locked, the pin’s output is HIGH with narrow low pulses.
8
10
f
IN
CLOCK
I
Prescaler input. Small signal input from the VCO.
9
11
I
High impedance CMOS Clock input. Data is clocked in on the rising edge, into the
various counters and registers.
10
13
DATA
I
Binary serial data input. Data entered MSB first. LSB is control bit. High impedance
CMOS input.
11
14
LE
I
Load enable input (with internal pull-up resistor). When LE transitions HIGH, data
stored in the shift registers is loaded into the appropriate latch (control bit
dependent). Clock must be low when LE toggles high or low. See Serial Data Input
Timing Diagram.
12
15
FC
I
Phase control select (with internal pull-up resistor). When FC is LOW, the polarity of
the phase comparator and charge pump combination is reversed.
X
16
BISW
O
Analog switch output. When LE is HIGH, the analog switch is ON, routing the
internal charge pump output through BISW (as well as through D
o
).
Monitor pin of phase comparator input. CMOS output.
13
17
f
OUT
w
p
O
14
18
O
Output for external charge pump.
w
p
is an open drain N-channel transistor and
requires a pull-up resistor.
15
19
PWDN
I
Power Down (with internal pull-up resistor).
PWDN
e
HIGH for normal operation.
PWDN
e
LOW for power saving.
Power down function is gated by the return of the charge pump to a TRI-STATE
condition.
16
20
w
r
NC
O
Output for external charge pump.
w
r
is a CMOS logic output.
No connect.
X
2,9,12
2