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參數(shù)資料
| 型號： | LMX1600TM/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 2000 MHz, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 631K |
| 代理商： | LMX1600TM/NOPB |
2.0 Programming Description (Continued)
2.2.2
MAIN_R REGISTER
If the Control Bits (CTL [1:0]) are 1 0 when LE transitions high, data is transferred from the 18-bit shift register into a latch which
sets the Main PLL 12-bit R counter divide ratio and various control functions. The divide ratio is programmed using the bits
MAIN_R_CNTR as shown in table 2.2.3. The divider ratio must be
≥ 2. The charge pump control word (CP_WORD[3:0] ) sets the
charge pump gain and the phase detector polarity as detailed in 2.4.
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
987654321
0
MAIN_R
CP_WORD[3:0]
MAIN_R_CNTR[11:0]
1
0
2.2.3
12-Bit Programmable Main and Auxiliary Reference Divider Ratio
(MAIN/AUX R Counter)
MAIN_R_CNTR/AUX_R_CNTR
Divide Ratio
11
10
987654321
0
2
00000000001
0
3
00000000001
1
4,095
11111111111
1
Note 7: Legal divide ratio: 2 to 4,095.
2.3
PROGRAMMABLE FEEDBACK (N) DIVIDERS
2.3.1
AUX_N Register
If the Control Bits ( CTL[1:0]) are 0 1 when LE transitions high, data is transferred from the 18-bit shift register into the AUX_N
register latch which sets the Aux PLL 16-bit programmable N counter value. The AUX_N counter is a 16-bit counter which is fully
programmable from 240 to 65,535 for 1.1 GHz option or from 56 to 32,767 for 500 MHz option. The AUX_N register consists of
the 4-bit swallow counter (AUX_A_CNTR), the 12-bit programmable counter (AUX_B_CNTR). Serial data format is shown below.
The divide ratio (AUX_N_CNTR [13:0]) must be
≥ 240 (1.1 GHz option) or ≥ 56 (500 MHz option) for a continuous divide range.
The Aux PLL N divide ratio is programmed using the bits AUX_A_CNTR, AUX_B_CNTR as shown in tables 2.3.2.
First Bit
SHIFT REGISTER BIT LOCATION
Last Bit
17
16
15
14
13
12
11
10
987654321
0
AUX_N
AUX_B_CNTR[11:0]
AUX_A_CNTR[3:0]
0
1
2.3.2
4-BIT Swallow Counter Divide Ratio (Aux A COUNTER)
1.1 GHz option
Swallow
AUX_A_CNTR
Count
(A)
3
2
1
0
00
0
10
0
1
15
1
Note 8: Swallow Counter Value: 0 to 15
500 MHz option
Swallow
AUX_A_CNTR
Count
(A)
3
2
1
0
0X
0
Swallow
AUX_A_CNTR
Count
(A)
3
2
1
0
1X
0
1
7X
1
Note 9: Swallow Counter Value: 0 to 7
X = Don’t Care condition
LMX1600/LMX1601/LMX1602
www.national.com
8
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